PAGE_MODE

Normal Paging

{0|1<PERSISTENCE_LEVEL>}

0

–

10 (address is TLLI)

– TLLI

same value as received from MS since GPRS attached

0, message escape

MAC_MODE

Extended Dynamic Allocation

RLC_MODE

acknowledged mode

CONTROL_ACK

0

TIMESLOT_ALLOCATION

single slot arbitrarily chosen from valid values, default slot 2

Packet Timing Advance

– {0|1<TIMING_ADVANCE_VALUE>}

1 (presence of the timing advance value)

– TIMING_ADVANCE_VALUE

30 bit periods

– {0|1<TIMING_ADVANCE_INDEX> <TIMING_ADVANCE_TIMESLOT_NUMBER >}

0 (no timing advance index)

– {0|1<P0><BTS_PWR_CTRL_MODE>}

0

{0|1<Frequency Parameters>}

0 (Frequency Parameters not present)

{0|1<DOWNLINK_TFI_ASSIGNMENT>}

1 (assign downlink TFI)

– DOWNLINK_TFI_ASSIGNMENT

Arbitrarily chosen from valid values (default 3)

{0|1<Power Control Parameters>}

1 (Power Control Parameters present)

– ALPHA

0.5

– {0|1<GAMMA_TN0>}

Depending on the value in TIMESLOT_ALLOCATION (default 0 no GAMMA_TN0)

– {0|1<GAMMA_TN1>}

Depending on the value in TIMESLOT_ALLOCATION (default 0 no GAMMA_TN1)

– {0|1<GAMMA_TN2>}

Depending on the value in TIMESLOT_ALLOCATION (default 1 GAMMA_TN2)

– GAMMA_TN2

For GSM 700, T-GSM 810, GSM 850 and GSM 900, +8 dBm

For DCS 1 800, +6 dBm

For PCS 1 900, +6 dBm

– {0|1<GAMMA_TN3>}

Depending on the value in TIMESLOT_ALLOCATION (default 0 no GAMMA_TN0)

– {0|1<GAMMA_TN4>}

Depending on the value in TIMESLOT_ALLOCATION (default 0 no GAMMA_TN4)

– {0|1<GAMMA_TN5>}

Depending on the value in TIMESLOT_ALLOCATION (default 0 no GAMMA_TN5)

– {0|1<GAMMA_TN6>}

Depending on the value in TIMESLOT_ALLOCATION (default 0 no GAMMA_TN6)

– {0|1<GAMMA_TN7>}

Depending on the value in TIMESLOT_ALLOCATION (default 0 no GAMMA_TN7)

{0|1<TBF_STARTING_TIME>}

1 (starting time present)

– TBF_STARTING_TIME

0, absolute frame number encoding,

indicating (current frame + 13 frames)

{0|1<Measurement Mapping>}

0 (no measurement mapping)

spare padding

Spare Padding

PAGE_MODE

Normal Paging

0<GLOBAL_TFI>

0

The TFI value of the uplink TBF or downlink TBF which this message applies to (default 00101)

0, message escape

CHANNEL_CODING_COMMAND

arbitrarily chosen from valid values (default CS-1)

Global Packet Timing Advance

– {0|1<TIMING_ADVANCE_VALUE>}

1 (timing advance value present)

– TIMING_ADVANCE_VALUE

30 bit periods

– {0|1<UPLINK_TIMING_ADVANCE_INDEX> <UPLINK_TIMING_ADVANCE_TIMESLOT_NUMBER>}

0 (no uplink timing advance index)

The MS stops the operation of the continuous timing advance procedure.

– {0|1<DOWNLINK_TIMING_ADVANCE_INDEX> <DOWNLINK_TIMING_ADVANCE_TIMESLOT_NUMBER>}

0 (no downlink timing advance index)

The MS stops the operation of the continuous timing advance procedure.

DOWNLINK_RLC_MODE

Same as in the Test PDP context used

CONTROL_ACK

0

{0|1<DOWNLINK_TFI_ASSIGNMENT>

0

{0|1<UPLINK_TFI_ASSIGNMENT>

0

DOWNLINK_TIMESLOT_ALLOCATION

arbitrarily chosen from valid values (default00010000)

{0|1<Frequency Parameters>}

0 (use current parameters)

Dynamic allocation

0

– Extended Dynamic Allocation

1 (Extended Dynamic Allocation)

– {0|1<P0><PR_MODE>}

0

– USF_GRANULARITY

0, one block

– {0|1<RLC_DATA_BLOCKS_GRANTED>}

0 (no RLC_DATA_BLOCKS_GRANTED, open-ended TBF)

– {0|1<TBF_STARTING_TIME>}

1 (starting time)

– TBF_STARTING_TIME

1, relative frame number encoding

indicating current frame + 104 by absolute encoding

–

1 (Timeslot Allocation with Power Control Parameters) one slot arbitrarily chosen and different from current slot, the following USF_TNx and GAMMA_TNx shall be corresponding to the chosen value, default timeslot 3.

– ALPHA

0.5

– {0|1<USF_TN0><GAMMA_TN0>}

0 (timeslot 0 not assigned)

– {0|1<USF_TN1><GAMMA_TN1>}

0 (timeslot 1 not assigned)

– {0|1<USF_TN2><GAMMA_TN2>}

0 (timeslot 2 not assigned)

– {0|1<USF_TN3><GAMMA_TN3>}

1 (timeslot 3 assigned)

– USF_TN3

arbitrarily chosen and different from current value, (default 4)

– GAMMA_TN3

For GSM 700, T-GSM 810, GSM 850 and GSM 900, +8 dBm

For DCS 1 800, +6 dBm

For PCS 1 900, +6 dBm

– {0|1<USF_TN4><GAMMA_TN4>}

1 (timeslot 4 assigned)

– USF_TN4

Arbitrarily chosen (default 3) but it must be different than USF_TN3

– GAMMA_TN4

For GSM 700, T-GSM 810, GSM 850 and GSM 900, +8 dBm

For DCS 1 800, +6 dBm

For PCS 1 900, +6 dBm

– {0|1<USF_TN5><GAMMA_TN5>}

1 (timeslot 5 assigned), if the MS supports at least 3 timeslots uplink

0 (timeslot 5 not assigned), if the MS supports only 2 timeslots uplink

– USF_TN5

Only if timeslot 5 is assigned

Arbitrarily chosen (default 2) but it must be different to USF_TN3 and USF_TN4

– GAMMA_TN5

For GSM 700, T-GSM 810, GSM 850 and GSM 900, +8 dBm

For DCS 1 800, +6 dBm

For PCS 1 900, +6 dBm

– {0|1<USF_TN6><GAMMA_TN6>}

1 (timeslot 6 assigned), if the MS supports at least 4 timeslots uplink

0 (timeslot 6 not assigned), if the MS supports less than 4 timeslots uplink

– USF_TN6

Only if timeslot 6 is assigned

arbitrarily chosen (default 1) but it must be different to USF_TN3, USF_TN4 and USF_TN5

– GAMMA_TN6

For GSM 700, T-GSM 810, GSM 850 and GSM 900, +8 dBm

For DCS 1 800, +6 dBm

For PCS 1 900, +6 dBm

– {0|1<USF_TN7><GAMMA_TN7>}

0 (timeslot 7 not assigned)

spare padding

Spare Padding

PAGE_MODE

Normal Paging

{0|1<PERSISTENCE_LEVEL>}

0 (no persistence level present)

– Address information

10 (TLLI)

– TLLI

The value received from the MS

0, message escape

CHANNEL_CODING_COMMAND

Arbitrarily chosen from the valid values (default CS-1)

TLLI_BLOCK_CHANNEL_CODING

‘0’B, cs-1

Packet Timing Advance

– {0|1<TIMING_ADVANCE_VALUE>}

1 (timing advance value)

– TIMING_ADVANCE_VALUE

30 bit periods

– {0|1<TIMING_ADVANCE_INDEX> <TIMING_ADVANCE_TIMESLOT_NUMBER >}

0 (no timing advance index)

{0|1<Frequency Parameters>}

0 (Frequency Parameters not present)

Dynamic allocation

01

– Extended Dynamic Allocation

1 (Extended Dynamic allocation)

– {0|1<P0><PR_MODE>}

0

– USF_GRANULARITY

0, one block

– {0|1<UPLINK_TFI_ASSIGNMENT>}

1 ( uplink TFI assignment)

– UPLINK_TFI_ASSIGNMENT

Arbitrarily chosen (default 00101)

– {0|1<RLC_DATA_BLOCKS_GRANTED>}

0 (no RLC_DATA_BLOCKS_GRANTED, open-ended TBF)

– {0|1<TBF_STARTING_TIME>}

0 (no starting time)

–

1 (Timeslot Allocation with Power Control Parameters) one slot arbitrarily chosen and the following USF_TNx and GAMMA_TNx shall be corresponding to the chosen value, default timeslot 2 assigned)

– ALPHA

0.5

– {0|1<USF_TN0><GAMMA_TN0>}

0 (timeslot 0 not assigned)

– {0|1<USF_TN1><GAMMA_TN1>}

0 (timeslot 1 not assigned)

– {0|1<USF_TN2><GAMMA_TN2>}

1 (timeslot 2 assigned)

– USF_TN2

Arbitrarily chosen (default 5)

– GAMMA_TN2

For GSM 700, T-GSM 810, GSM 850 and GSM 900, +8 dBm

For DCS 1 800, +6 dBm

For PCS 1 900, +6 dBm

– {0|1<USF_TN3><GAMMA_TN3>}

1 (timeslot 3 assigned)

– USF_TN3

Arbitrarily chosen (default 6) but it must be different than USF_TN2

– GAMMA_TN3

For GSM 700, T-GSM 810, GSM 850 and GSM 900, +8 dBm

For DCS 1 800, +6 dBm

For PCS 1 900, +6 dBm

– {0|1<USF_TN4><GAMMA_TN4>}

1 (timeslot 4 assigned), if the MS supports at least 3 timeslots uplink

0 (timeslot 4 not assigned), if the MS supports only 2 timeslots uplink

– USF_TN4

Only if timeslot 4 is assigned

Arbitrarily chosen (default 4) but it must be different to USF_TN2 and USF_TN3

– GAMMA_TN4

Only if timeslot 4 is assigned

For GSM 700, T-GSM 810, GSM 850 and GSM 900, +8 dBm

For DCS 1 800, +6 dBm

For PCS 1 900, +6 dBm

– {0|1<USF_TN5><GAMMA_TN5>}

1 (timeslot 5 assigned), if the MS supports at least 4 timeslots uplink

0 (timeslot 5 not assigned), if the MS supports less than 4 timeslots uplink

– USF_TN5

Only if timeslot 5 is assigned

Arbitrarily chosen (default 3) but it must be different to USF_TN2, USF_TN3 and USF_TN4

– GAMMA_TN5

Only if timeslot 5 is assigned

For GSM 700, T-GSM 810, GSM 850 and GSM 900, +8 dBm

For DCS 1 800, +6 dBm

For PCS 1 900, +6 dBm

– {0|1<USF_TN6><GAMMA_TN6>}

0 (timeslot 6 not assigned)

– {0|1<USF_TN7><GAMMA_TN7>}

0 (timeslot 7 not assigned)

spare padding

Spare Padding

1

{Uplink dynamic allocation two phase access}

n = 1500 octets, without starting time,

Up to 4 timeslots are assigned according to MS multislot class (TS 5.02 Annex B.1) :

– USF₁ on TN₁,

– USF₂ on TN₂,

– USF₃ on TN₃,

– USF₄ on TN₄,

Default PACKET UPLINK ASSIGNMENT message content for EDA defined in sub-clause 42.9.1 shall be used.

2

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCK

Assigned USF₁ on PACCH₁ addressing the MS on 3 blocks from the last radio block containing the uplink assignment.

3

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCK

USF on PACCH₂ is not addressing the MS, sent on the same TDMA frame as step 2.

4

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCK

This step is optional; it is performed only if 3 timeslots at least have been assigned in step 1.

USF on PACCH₃ is not addressing the MS, sent on the same TDMA frame as step 2.

5

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCK

This step is optional; it is performed only if 4 timeslots have been assigned in step 1.

USF on PACCH₄ is not addressing the MS, sent on the same TDMA frame as step 2.

6

MS -> SS

UPLINK RLC DATA BLOCK

Received on the assigned PDTCH₁.

7

MS -> SS

UPLINK RLC DATA BLOCK

Received on the assigned PDTCH₂ on the same TDMA frame as step 6.

8

MS -> SS

UPLINK RLC DATA BLOCK

This step is optional; it is performed only if 3 timeslots at least have been assigned in step 1.Received on the assigned PDTCH₃ on the same TDMA frame as step 6.

9

MS -> SS

UPLINK RLC DATA BLOCK

This step is optional; it is performed only if 4 timeslots have been assigned in step 1.

Received on the assigned PDTCH₄ on the same TDMA frame as step 6.

10

SS -> MS

PACKET UPLINK ACK/NACK

Assigned USF₁ on PACCH₁ addressing the MS.

11

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCK

USF on PACCH₂ is not addressing the MS, sent on the same TDMA frame as step 10

12

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCK

This step is optional; it is performed only if 3 timeslots at least have been assigned in step 1.

USF on PACCH₃ is not addressing the MS, sent on the same TDMA frame as step 10

13

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCK

This step is optional; it is performed only if 4 timeslots have been assigned in step 1.

USF on PACCH₄ is not addressing the MS, sent on the same TDMA frame as step 10

14

MS -> SS

UPLINK RLC DATA BLOCK

Received on the assigned PDTCH₁.

15

MS -> SS

UPLINK RLC DATA BLOCK

Received on the assigned PDTCH₂ on the same TDMA frame as step 14

16

MS -> SS

UPLINK RLC DATA BLOCK

This step is optional; it is performed only if 3 timeslots at least have been assigned in step 1.

Received on the assigned PDTCH₃ on the same TDMA frame as step 14.

17

MS -> SS

UPLINK RLC DATA BLOCK

This step is optional; it is performed only if 4 timeslots have been assigned in step 1.

Received on the assigned PDTCH₄ on the same TDMA frame as step 14.

18

{Completion of uplink RLC data block transfer in extended dynamic mode}

19

{Uplink dynamic allocation two phase access}

n = 1500 octets, without starting time,

Up to 4 timeslots are assigned according to MS multislot class (TS 5.02 Annex B.1):

– USF₁ on TN₁,

– USF₂ on TN₂,

– USF₃ on TN₃,

– USF₄ on TN₄,

Default PACKET UPLINK ASSIGNMENT message content for EDA defined in sub-clause 42.9.1 shall be used.

20

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCK

USF on PACCH₁ is not addressing the MS

21

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCK

This step is optional; it is performed only if 3 timeslots at least have been assigned in step 19.

USF on PACCH₂ is not addressing the MS, sent on the same TDMA frame as step 20.

22

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCK

This step is optional; it is performed only if 4 timeslots have been assigned in step 19.

USF on PACCH₃ is not addressing the MS, sent on the same TDMA frame as step 20.

23

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCK

Assigned USF_N on PACCH_N addressing the MS, where N is the number of assigned timeslots in step 19, sent on the same TDMA frame as step 20.

24

MS->SS

It is checked that no UPLINK RLC DATA BLOCK messages are received on the assigned PDTCH₁ to PDTCH_N-1.

25

MS -> SS

UPLINK RLC DATA BLOCK

Received only on the assigned PDTCH_N.

26

SS -> MS

PACKET UPLINK ACK/NACK

USF on PACCH₁ is not addressing the MS

27

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCK

This step is optional; it is performed only if 3 timeslots at least have been assigned in step 19.

USF on PACCH₂ is not addressing the MS, sent on the same TDMA frame as step 26.

28

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCK

This step is optional; it is performed only if 4 timeslots have been assigned in step 19.

USF on PACCH₃ is not addressing the MS, sent on the same TDMA frame as step 26.

29

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCK

Assigned USF_N on PACCH_N addressing the MS, where N is the number of assigned timeslots in step 19, sent on the same TDMA frame as step 26.

30

MS->SS

It is checked that no UPLINK RLC DATA BLOCK messages are received on the assigned PDTCH₁ to PDTCH_N-1.

31

MS -> SS

UPLINK RLC DATA BLOCK

Received only on the assigned PDTCH_N

32

{Completion of uplink RLC data block transfer in extended dynamic mode}

1

{Uplink dynamic allocation two phase access}

n = 1500 octets, without starting time,

2 timeslots are assigned

– USF₁ on PDCH₁,

– USF₂ on PDCH₂,

– USF_GRANULARITY = 1 (4 blocks)

Default PACKET UPLINK ASSIGNMENT message content for EDA defined in sub-clause 42.9.1 shall be used.

2

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCK

USF₁ on block N₁ of PACCH₁ is addressing the MS (must be at least 3 blocks after the block containing the uplink assignment.)

3

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCK

USF on block N₁ of PACCH₂ is NOT addressing the MS.

4

MS -> SS

UPLINK RLC DATA BLOCK

Received on block N₁+1 of PDTCH₁

5

MS -> SS

UPLINK RLC DATA BLOCK

Received on block N₁+1 of PDTCH₂

6

MS -> SS

UPLINK RLC DATA BLOCK

Received on block N₁+2 of PDTCH₁

7

MS -> SS

UPLINK RLC DATA BLOCK

Received on block N₁+2 of PDTCH₂

8

MS -> SS

UPLINK RLC DATA BLOCK

Received on block N₁+3 of PDTCH₁

9

MS -> SS

UPLINK RLC DATA BLOCK

Received on block N₁+3 of PDTCH₂

10

MS -> SS

UPLINK RLC DATA BLOCK

Received on block N₁+4 of PDTCH₁

11

MS -> SS

UPLINK RLC DATA BLOCK

Received on block N₁+4 of PDTCH₂

12

SS -> MS

PACKET UPLINK ACK/NACK

Acknowledge all received data blocks, on block N₂ of PACCH₁

With: S/P=1, RRBP = 0, and USF₁

13

MS -> SS

UPLINK RLC DATA BLOCK

Received on block N₂+1 of PDTCH₁

14

MS -> SS

UPLINK RLC DATA BLOCK

Received on block N₂+1 of PDTCH₂

15

MS -> SS

UPLINK RLC DATA BLOCK

Received on block N₂+2 of PDTCH₁

16

MS -> SS

UPLINK RLC DATA BLOCK

Received on block N₂+2 of PDTCH₂

17

MS -> SS

PACKET CONTROL ACKNOWLEDGEMENT

Received on block N₂+3 of PACCH₁

18

MS -> SS

UPLINK RLC DATA BLOCK

Received on block N₂+3 of PDTCH₂

19

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCK

USF₁ on block N₂ + 4 of PACCH₁ is addressing the MS.

20

MS -> SS

UPLINK RLC DATA BLOCK

Received on block N₂+4 of PDTCH₁

21

MS -> SS

UPLINK RLC DATA BLOCK

Received on block N₂+4 of PDTCH₂

22

MS -> SS

UPLINK RLC DATA BLOCK

Received on block N₂+5 of PDTCH₁

23

MS -> SS

UPLINK RLC DATA BLOCK

Received on block N₂+5 of PDTCH₂

24

MS -> SS

UPLINK RLC DATA BLOCK

Received on block N₂+6 of PDTCH₁

25

MS -> SS

UPLINK RLC DATA BLOCK

Received on block N₂+6 of PDTCH₂

26

MS -> SS

UPLINK RLC DATA BLOCK

Received on block N₂+7 of PDTCH₁

27

MS -> SS

UPLINK RLC DATA BLOCK

Received on block N₂+7 of PDTCH₂

28

MS -> SS

UPLINK RLC DATA BLOCK

Received on block N₂+8 of PDTCH₁

29

MS -> SS

UPLINK RLC DATA BLOCK

Received on block N₂+8 of PDTCH₂

30

{Completion of uplink RLC data block transfer in extended dynamic mode}

1

{Uplink dynamic allocation two phase access}

n = 1500 octets, without starting time,

Up to 3 timeslots are assigned according to MS multi-slot class (TS 5.02 Annex B.1) :

• USF₁ on PDCH₁,
• USF₂ on PDCH₂,
• USF₃ on PDCH₃,

2

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCK

USF₁ on block N₁ of PACCH₁ is addressing the MS (must be at least 3 blocks after the block containing the uplink assignment.)

3

MS -> SS

UPLINK RLC DATA BLOCK

Received on block N₁+1 of PDTCH₁

4

MS -> SS

UPLINK RLC DATA BLOCK

Received on block N₁+1 of PDTCH₂

5

MS -> SS

UPLINK RLC DATA BLOCK

This step is optional, it is performed only if 3 timeslots have been allocated in step 1

Received on block N₁+1 of PDTCH₃

6

SS -> MS

PACKET UPLINK ACK/NACK

Acknowledge all received data blocks, on block N₂ of PACCH₁

With: S/P=1, RRBP = 0

USF is NOT addressing the MS

7

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCK

USF₁ on block N₂+2 of PACCH₁ is addressing the MS

8

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCK

USF₁ on block N₂+3 of PACCH₁ is addressing the MS

9

MS -> SS

PACKET CONTROL ACKNOWLEDGEMENT

Received on block N₂+3 of PACCH₁

10

MS -> SS

UPLINK RLC DATA BLOCK

Received on block N₂+3 of PDTCH₂

11

MS -> SS

UPLINK RLC DATA BLOCK

This step is optional, it is performed only if 3 timeslots have been allocated in step 1

Received on block N₂+3 of PDTCH₃

12

MS -> SS

UPLINK RLC DATA BLOCK

Received on block N₂+4 of PDTCH₁

13

MS -> SS

UPLINK RLC DATA BLOCK

Received on block N₂+4 of PDTCH₂

14

MS -> SS

UPLINK RLC DATA BLOCK

This step is optional, it is performed only if 3 timeslots have been allocated in step 1

Received on block N₂+4 of PDTCH₃

15

SS -> MS

PACKET UPLINK ACK/NACK

Acknowledge all received data blocks, on block N₃ of PACCH₁

With: S/P=1, RRBP = 0

USF is NOT addressing the MS

16

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCK

USF on block N₃+3 of PACCH₁ is NOT addressing the MS

17

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCK

USF₂ on block N₃+3 of PACCH₂ is addressing the MS

18

MS -> SS

PACKET CONTROL ACKNOWLEDGEMENT

Received on block N₃+3 of PACCH₁

19

MS -> SS

UPLINK RLC DATA BLOCK

Received on block N₃+4 of PDTCH₂

20

MS -> SS

UPLINK RLC DATA BLOCK

This step is optional, it is performed only if 3 timeslots have been allocated in step 1

Received on block N₃+4 of PDTCH₃

The steps below are applicable only for the MS multi-slot class 7, 11, 12, 20 to 23, 25 to 29, 33, 34, 38, 39

21

SS -> MS

PACKET UPLINK ACK/NACK

Acknowledge all received data blocks, on block N₄ of PACCH₁

With: S/P=1, RRBP = 0

USF is NOT addressing the MS

22

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCK

USF on block N₄+3 of PACCH₁ is NOT addressing the MS

23

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCK

USF on block N₄+3 of PACCH₂ is NOT addressing the MS

24

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCK

USF₃ on block N₄+3 of PACCH₃ is addressing the MS

25

MS -> SS

PACKET CONTROL ACKNOWLEDGEMENT

Received on block N₄+3 of PACCH₁

26

Verify that the MS does not transmit any RLC data block

27

{Completion of uplink RLC data block transfer in extended dynamic mode}

3

1

2

5

2

2

6

2

2

7

2

2

9

3

2

10

3

2

11

3

2

12

3

2

13

3

3

14

4

4

15

5

5

16

6

6

17

7

7

18

8

8

19

6

2

20

6

3

21

6

4

22

6

4

23

6

6

24

8

2

25

8

3

26

8

4

27

8

4

28

8

6

29

8

8

31

4

2

32

3

3

33

3

3

34

3

3

36

4

2

37

3

3

38

3

3

39

3

3

41

5

2

42

4

3

43

4

3

44

4

3

45

4

3

1

{Uplink dynamic allocation two phase access}

Default PACKET UPLINK ASSIGNMENT message content for EDA defined in sub-clause 42.9.1shall be used.

n = 1500 octets, without starting time,

2

SS -> MS

PACKET DOWNLINK ASSIGNMENT

Default PACKET DOWNLINK ASSIGNMENT message content for EDA defined in sub-clause 42.9.1shall be used.

Sent on the PACCH of the lowest PDCH of the uplink PDCH allocation.

Including the Polling bit set and a valid RRBP field.

Including the TFI assigned to the uplink TBF.

3

MS -> SS

PACKET CONTROL ACKNOWLEDGEMENT

Received on the PACCH of the lowest PDCH of the uplink PDCH allocation.

4

SS

The SS verifies that the MS sends the PACKET CONTROL ACKNOWLEDGEMENT message, on the uplink radio block specified by the RRBP of the lowest PDCH of the uplink PDCH allocation.

5

SS -> MS

DOWNLINK GPRS RLC DATA BLOCK

Sent on the highest PDCH of the uplink PDCH allocation.

Including the USF assigned to the MS on the highest PDCH of the uplink PDCH allocation.

Including an invalid RRBP.

6

MS -> SS

UPLINK GPRS RLC DATA BLOCK

Received on the highest PDCH of the uplink PDCH allocation.

SI=0

7

Repeat steps 5 and 6 for BSN=1 to 63.

SS doesn’t acknowledge any of the GPRS RLC data blocks with BSN from 0 to 63 (see note below).

8

SS -> MS

DOWNLINK GPRS RLC DATA BLOCK

Sent on the highest PDCH of the uplink PDCH allocation.

Including the USF assigned to the MS on the highest PDCH of the uplink PDCH allocation.

Including an invalid RRBP.

9

MS -> SS

UPLINK GPRS RLC DATA BLOCK

Received on the highest PDCH of the uplink PDCH allocation.

SI=1

10

SS->MS

PACKET UPLINK ACK/NACK

SS acknowledges the oldest GPRS RLC data block.

Sent on the PACCH of the lowest PDCH of the uplink PDCH allocation.

Including the TFI assigned to the uplink TBF.

Including an USF not assigned to the MS on this PDCH.

Wait for 6 blocks with no assigned USF

11

SS -> MS

DOWNLINK GPRS RLC DATA BLOCK

Sent on the highest PDCH of the uplink PDCH allocation.

Including the USF assigned to the MS on the highest PDCH of the uplink PDCH allocation.

Including an invalid RRBP.

12

MS -> SS

UPLINK GPRS RLC DATA BLOCK

Received on the highest PDCH of the uplink PDCH allocation.

13

SS

The steps 11 and 12 are repeated k times <=8 until V(R) has been incremented by one (i.e. the MS has correctly understood the PACKET UPLINK ACK/NACK).

14

SS -> MS

DOWNLINK GPRS RLC DATA BLOCK

Sent on the highest PDCH of the uplink PDCH allocation.

Including the USF assigned to the MS on the highest PDCH of the uplink PDCH allocation.

Including an invalid RRBP.

15

MS -> SS

UPLINK GPRS RLC DATA BLOCK

Received on the highest PDCH of the uplink PDCH allocation.

16

The steps 14 and 15 are repeated until a RLC DATA BLOCK with SI=1 is received (see note below).

17

SS->MS

PACKET UPLINK ACK/NACK

SS acknowledges the oldest GPRS RLC data block.

Sent on a PDCH common to the downlink and uplink PDCH allocation.

Including the TFI of the uplink TBF.

Including an USF not assigned to the MS on this PDCH.

Wait for 6 blocks with no assigned USF

18

SS -> MS

DOWNLINK GPRS RLC DATA BLOCK

Sent on the highest PDCH of the uplink PDCH allocation.

Including the USF assigned to the MS on this PDCH.

Including an invalid RRBP.

19

MS -> SS

UPLINK GPRS RLC DATA BLOCK

Received on the highest PDCH of the uplink PDCH allocation.

20

SS

The steps 18 and 19 are repeated k times <=8 until V(R) has been incremented by one (i.e. the MS has correctly understood the PACKET UPLINK ACK/NACK).

21

SS -> MS

DOWNLINK GPRS RLC DATA BLOCK

Sent on the highest PDCH of the uplink PDCH allocation.

Including the USF assigned to the MS on the highest PDCH of the uplink PDCH allocation.

Including an invalid RRBP.

22

MS -> SS

UPLINK GPRS RLC DATA BLOCK

Received on the highest PDCH of the uplink PDCH allocation.

23

The steps 21 and 22 are repeated until a RLC DATA BLOCK with SI=1 is received (see note below).

24

The steps 17, 18, 19, 20, 21, 22 and 23 are repeated for each PDCH common to the downlink and uplink PDCH allocation.

25

SS->MS

PACKET UPLINK ACK/NACK

SS acknowledges all RLC data block.

Sent on a PDCH common to the downlink and uplink PDCH allocation.

Including the Polling bit set and a valid RRBP field

Including the TFI assigned to the uplink TBF.

26

SS -> MS

DOWNLINK GPRS RLC DATA BLOCK

Sent on the lowest PDCH of the uplink PDCH allocation on the block period preceding the response to the polling requested in step 25.

Including the USF assigned to the MS on this PDCH.

27

MS -> SS

UPLINK GPRS RLC/MAC BLOCK

Received during the block period where the polling response should be sent.

An UPLINK RLC CONTROL BLOCK should be received on the PDCH where the MS is polled or an UPLINK RLC DATA BLOCK should be received on the other PDCHs.

28

The step 27 is repeated a number of times equal to the number of PDCHs of the uplink PDCH allocation to get all RLC/MAC BLOCK sent by the MS.

29

SS

Verify that the MS did not transmit a RLC data block on the reserved uplink radio block specified by the RRBP on the PDCH where it has been polled. A PACKET CONTROL ACKNOWLEDGEMENT shall be transmitted instead.

Verify that the MS has transmitted RLC data blocks on the other PDCHs.

30

The steps 25, 26, 27, 28 and 29 are repeated for each PDCH common to the downlink and uplink PDCH allocation.

31

SS -> MS

DOWNLINK GPRS RLC DATA BLOCK

Sent on a PDCH common to the downlink and uplink PDCH allocation.

Including a valid RRBP and FBI = 1.

Including an USF not assigned to the MS on this PDCH.

32

MS -> SS

PACKET DOWNLINK ACK/NACK

33

{Completion of uplink RLC data block transfer in extended dynamic mode}

3

1

2

5

2

2

6

2

2

7

2

2

9

3

2

10

3

2

11

3

2

12

3

2

13

3

3

14

4

4

15

5

5

16

6

6

17

7

7

18

8

8

19

6

2

20

6

3

21

6

4

22

6

4

23

6

6

24

8

2

25

8

3

26

8

4

27

8

4

28

8

6

29

8

8

31

4

2

32

3

3

33

3

3

34

3

3

36

4

2

37

3

3

38

3

3

39

3

3

41

5

2

42

4

3

43

4

3

44

4

3

45

4

3

1

{Uplink dynamic allocation two phase access}

Default PACKET UPLINK ASSIGNMENT message content for EDA defined in sub-clause 42.9.1shall be used.

n = 20 octets, without starting time

2

SS -> MS

PACKET DOWNLINK ASSIGNMENT

Default PACKET DOWNLINK ASSIGNMENT message content for EDA defined in sub-clause 42.9.1shall be used.

Sent on the PACCH of the lowest PDCH of the uplink PDCH allocation.

Including the polling bit set and a valid RRBP field.

Including the TFI assigned to the uplink TBF.

3

MS -> SS

PACKET CONTROL ACKNOWLEDGEMENT

Received on the PACCH of the lowest PDCH of the uplink PDCH allocation.

4

SS -> MS

DOWNLINK GPRS RLC DATA BLOCK

Sent on a PDCH common to the downlink and uplink PDCH allocation.

Including the Polling bit set and a valid RRBP field.

Including the TFI assigned to the uplink TBF.

5

MS -> SS

PACKET DOWNLINK ACK/NACK

Received on the same PDCH and on the uplink radio block specified by the RRBP.

6

SS

The SS verifies that the MS sends a PACKET DOWNLINK ACK/NACK acknowledging the GPRS RLC data block.

7

The steps 4, 5 and 6 are repeated with each PDCH common to the downlink and uplink PDCH allocation.

8

{Completion of uplink RLC data block transfer in extended dynamic mode}

1

{Uplink dynamic allocation two phase access}

N = 1500 octets, without starting time, Assigning the TBF in dynamic mode.

Up to 2 timeslots are assigned according to MS multislot class (TS 05.02 Annex B.1):

• USF₁ on TN₁,
• USF₂ on TN₂,

2

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCK

Assigned USF₁ on PACCH₁ addressing the MS sent on 3 blocks from the last radio block containing the uplink assignment.

3

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCK

This step is optional; it is performed only if 2 timeslots have been assigned in step 1.

Assigned USF₂ on PACCH₂ addressing the MS sent on the same TDMA frame as step 2.

4

MS -> SS

UPLINK RLC DATA BLOCK

Received on the assigned PDTCH₁.

5

MS -> SS

UPLINK RLC DATA BLOCK

This step is optional; it is performed only if 2 timeslots have been assigned in step 1.

Received on the assigned PDTCH₂ on the same TDMA frame as in step 4.

6

SS -> MS

PACKET UPLINK ACK/NACK

Assigned USF₁ on PACCH₁ addressing the MS.

7

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCK

This step is optional; it is performed only if 2 timeslots have been assigned in step 1.

USF on PACCH₂ is not addressing the MS, sent on the same TDMA frame as step 6

8

MS -> SS

UPLINK RLC DATA BLOCK

Received on the assigned PDTCH₁.

9

This step is optional; it is performed only if 2 timeslots have been assigned in step 1.

Check that the MS does not send the data on the PDTCH₂ as the USF sent on the PACCH_{2 in} step 7 is not addressing to the MS.

10

SS -> MS

PACKET UPLINK ASSIGNMENT

Sent on PACCH₁ addressing the MS, without starting time, assigning extended dynamic allocation.

Up to 4 timeslots are assigned according to MS multislot class (TS 05.02 Annex B.1):

• USF₁ on TN₁,
• USF₂ on TN₂,
• USF₃ on TN₃,
• USF₄ on TN₄,

11

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCK

Assigned USF₁ on PACCH₁ addressing the MS on 3 blocks from the last radio block containing the uplink assignment in step 10.

12

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCK

USF on PACCH₂ is not addressing the MS, sent on the same TDMA frame as step 11.

13

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCK

This step is optional; it is performed only if 3 timeslots at least have been assigned in step 10.

USF on PACCH₃ is not addressing the MS, sent on the same TDMA frame as step 11.

14

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCK

This step is optional; it is performed only if 4 timeslots have been assigned in step 10.

USF on PACCH₄ is not addressing the MS, sent on the same TDMA frame as step 11.

15

MS -> SS

UPLINK RLC DATA BLOCK

Received on the assigned PDTCH₁.

16

MS -> SS

UPLINK RLC DATA BLOCK

Received on the assigned PDTCH₂ on the same TDMA frame as step 15.

17

MS -> SS

UPLINK RLC DATA BLOCK

This step is optional; it is performed only if 3 timeslots at least have been assigned in step 10. Received on the assigned PDTCH₃ on the same TDMA frame as step 15.

18

MS -> SS

UPLINK RLC DATA BLOCK

This step is optional; it is performed only if 4 timeslots have been assigned in step 10.

Received on the assigned PDTCH₄ on the same TDMA frame as step 15.

19

SS -> MS

PACKET UPLINK ACK/NACK

Assigned USF₁ on PACCH₁ addressing the MS.

20

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCK

USF on PACCH₂ is not addressing the MS, sent on the same TDMA frame as step 19

21

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCK

This step is optional; it is performed only if 3 timeslots at least have been assigned in step 10.

USF on PACCH₃ is not addressing the MS, sent on the same TDMA frame as step 19

22

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCK

This step is optional; it is performed only if 4 timeslots have been assigned in step 10.

USF on PACCH₄ is not addressing the MS, sent on the same TDMA frame as step 19

23

MS -> SS

UPLINK RLC DATA BLOCK

Received on the assigned PDTCH₁.

24

MS -> SS

UPLINK RLC DATA BLOCK

Received on the assigned PDTCH₂ on the same TDMA frame as step 23

25

MS -> SS

UPLINK RLC DATA BLOCK

This step is optional; it is performed only if 3 timeslots at least have been assigned in step 10.

Received on the assigned PDTCH₃ on the same TDMA frame as step 23.

26

MS -> SS

UPLINK RLC DATA BLOCK

This step is optional; it is performed only if 4 timeslots have been assigned in step 10.

Received on the assigned PDTCH₄ on the same TDMA frame as step 23.

27

{Completion of uplink RLC data block transfer in extended dynamic mode}

1

{Uplink dynamic allocation two phase access}

N = 1500 octets, without starting time, Assigning the TBF in extended dynamic mode.

Up to 4 timeslots are assigned according to MS multislot class (TS 05.02 Annex B.1) :

• USF₁ on TN₁,
• USF₂ on TN₂,
• USF₃ on TN₃,
• USF₄ on TN₄,

2

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCK

Assigned USF₁ on PACCH₁ addressing the MS. Sent on third block from the last radio block containing the uplink assignment in step 1.

3

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCK

USF on PACCH₂ is not addressing the MS, sent on the same TDMA frame as step 2.

4

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCK

This step is optional; it is performed only if 3 timeslots at least have been assigned in step 1.

USF on PACCH₃ is not addressing the MS, sent on the same TDMA frame as step 2.

5

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCK

This step is optional; it is performed only if 4 timeslots have been assigned in step 1.

USF on PACCH₄ is not addressing the MS, sent on the same TDMA frame as step 2.

6

MS -> SS

UPLINK RLC DATA BLOCK

Received on the assigned PDTCH₁.

7

MS -> SS

UPLINK RLC DATA BLOCK

Received on the assigned PDTCH₂ on the same TDMA frame as step 6.

8

MS -> SS

UPLINK RLC DATA BLOCK

This step is optional; it is performed only if 3 timeslots at least have been assigned in step 1.

Received on the assigned PDTCH₃ on the same TDMA frame as step 6.

9

MS -> SS

UPLINK RLC DATA BLOCK

This step is optional; it is performed only if 4 timeslots have been assigned in step 1.

Received on the assigned PDTCH₄ on the same TDMA frame as step 6.

10

SS -> MS

PACKET UPLINK ACK/NACK

Assigned USF₁ on PACCH₁ addressing the MS.

11

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCK

USF on PACCH₂ is not addressing the MS, sent on the same TDMA frame as step 10

12

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCK

This step is optional; it is performed only if 3 timeslots at least have been assigned in step 1.

USF on PACCH₃ is not addressing the MS, sent on the same TDMA frame as step 10

13

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCK

This step is optional; it is performed only if 4 timeslots have been assigned in step 1.

USF on PACCH₄ is not addressing the MS, sent on the same TDMA frame as step 10

14

MS -> SS

UPLINK RLC DATA BLOCK

Received on the assigned PDTCH₁.

15

MS -> SS

UPLINK RLC DATA BLOCK

Received on the assigned PDTCH₂ on the same TDMA frame as step 14

16

MS -> SS

UPLINK RLC DATA BLOCK

This step is optional; it is performed only if 3 timeslots at least have been assigned in step 1.

Received on the assigned PDTCH₃ on the same TDMA frame as step 14.

17

MS -> SS

UPLINK RLC DATA BLOCK

This step is optional; it is performed only if 4 timeslots have been assigned in step 1.

Received on the assigned PDTCH₄ on the same TDMA frame as step 14.

18

PACKET UPLINK ASSIGNMENT

Reconfigures the TBF.

Up to 2 timeslots are assigned according to MS multislot class (TS 05.02 Annex B.1) :

• USF₁ on TN₁,
• USF₂ on TN₂,

19

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCK

Assigned USF₁ on PACCH₁ addressing the MS. Sent on third block from the last radio block containing the uplink assignment.

20

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCK

This step is optional; it is performed only if 2 timeslots have been assigned in step 18.

Assigned USF₂ on PACCH₂ addressing the MS sent on the same TDMA frame as step 19.

21

MS -> SS

UPLINK RLC DATA BLOCK

Received on the assigned PDTCH₁.

22

MS -> SS

UPLINK RLC DATA BLOCK

This step is optional; it is performed only if 2 timeslots have been assigned in step 18.

Received on the assigned PDTCH₂ on the same TDMA frame as step 21.

23

SS -> MS

PACKET UPLINK ACK/NACK

Assigned USF₁ on PACCH₁ addressing the MS.

24

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCK

This step is optional; it is performed only if 2 timeslots have been assigned in step 18.

USF on PACCH₂ is not addressing the MS, sent on the same TDMA frame as step 23

25

MS -> SS

UPLINK RLC DATA BLOCK

Received on the assigned PDTCH₁.

26

This step is optional; it is performed only if 2 timeslots have been assigned in step 18.

Check that the MS does not send the data on the PDTCH₂ as the USF sent on the PACCH_2, step 24 is not addressing to the MS.

27

{Completion of uplink RLC data block transfer}

1

{Uplink dynamic allocation two phase access}

N = 1500 octets, without starting time, Assigning the TBF in extended dynamic mode.

Up to 4 timeslots are assigned according to MS multislot class (TS 05.02 Annex B.1) :

• USF₁ on TN₁,
• USF₂ on TN₂,
• USF₃ on TN₃,
• USF₄ on TN₄,

2

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCK

Assigned USF₁ on PACCH₁ addressing the MS. Sent on third block from the last radio block containing the uplink assignment.

3

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCK

USF on PACCH₂ is not addressing the MS, sent on the same TDMA frame as step 2.

4

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCK

This step is optional; it is performed only if 3 timeslots at least have been assigned in step 1.

USF on PACCH₃ is not addressing the MS, sent on the same TDMA frame as step 2.

5

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCK

This step is optional; it is performed only if 4 timeslots have been assigned in step 1.

USF on PACCH₄ is not addressing the MS, sent on the same TDMA frame as step 2.

6

MS -> SS

UPLINK RLC DATA BLOCK

Received on the assigned PDTCH₁.

7

MS -> SS

UPLINK RLC DATA BLOCK

Received on the assigned PDTCH₂ on the same TDMA frame as step 6.

8

MS -> SS

UPLINK RLC DATA BLOCK

This step is optional; it is performed only if 3 timeslots at least have been assigned in step 1.Received on the assigned PDTCH₃ on the same TDMA frame as step 6.

9

MS -> SS

UPLINK RLC DATA BLOCK

This step is optional; it is performed only if 4 timeslots have been assigned in step 1.

Received on the assigned PDTCH₄ on the same TDMA frame as step 6.

10

SS -> MS

PACKET UPLINK ACK/NACK

Assigned USF₁ on PACCH₁ addressing the MS.

11

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCK

USF on PACCH₂ is not addressing the MS, sent on the same TDMA frame as step 10

12

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCK

This step is optional; it is performed only if 3 timeslots at least have been assigned in step 1.

USF on PACCH₃ is not addressing the MS, sent on the same TDMA frame as step 10

13

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCK

This step is optional; it is performed only if 4 timeslots have been assigned in step 1.

USF on PACCH₄ is not addressing the MS, sent on the same TDMA frame as step 10

14

MS -> SS

UPLINK RLC DATA BLOCK

Received on the assigned PDTCH₁.

15

MS -> SS

UPLINK RLC DATA BLOCK

Received on the assigned PDTCH₂ on the same TDMA frame as step 14

16

MS -> SS

UPLINK RLC DATA BLOCK

This step is optional; it is performed only if 3 timeslots at least have been assigned in step 1.

Received on the assigned PDTCH₃ on the same TDMA frame as step 14.

17

MS -> SS

UPLINK RLC DATA BLOCK

This step is optional; it is performed only if 4 timeslots have been assigned in step 1.

Received on the assigned PDTCH₄ on the same TDMA frame as step 14.

18

SS -> MS

PACKET UPLINK ASSIGNMENT

SS reconfigures the TBF. Assignment assigns a starting time of 104 frames. This assignment reduces the number of slots by one as compared to the earlier allocation given in step 1. the highest numbered PDCH assigned in step 1 is removed from the allocation.

19

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCK

Assigned USF₁ on PACCH₁ addressing the MS. Send on 3 blocks before the starting time given in step 18.

20

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCK

USF on PACCH₂ is not addressing the MS, sent on the same TDMA frame as step 19.

21

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCK

This step is optional; it is performed only if 3 timeslots at least have been assigned in step 1.

USF on PACCH₃ is not addressing the MS, sent on the same TDMA frame as step 19.

22

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCK

This step is optional; it is performed only if 4 timeslots have been assigned in step 1.

USF on PACCH₄ is not addressing the MS, sent on the same TDMA frame as step 19.

23

MS -> SS

UPLINK RLC DATA BLOCK

Received on the assigned PDTCH₁.

24

MS -> SS

UPLINK RLC DATA BLOCK

Received on the assigned PDTCH₂ on the same TDMA frame as step 23.

25

MS -> SS

UPLINK RLC DATA BLOCK

This step is optional; it is performed only if 3 timeslots at least have been assigned in step 1.Received on the assigned PDTCH₃ on the same TDMA frame as step 23.

26

MS -> SS

UPLINK RLC DATA BLOCK

This step is optional; it is performed only if 4 timeslots have been assigned in step 1.

Received on the assigned PDTCH₄ on the same TDMA frame as step 23.

27

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCK

Assigned USF addressing the MS. Sent on the highest numbered PDCH assigned in step 1. Send on next block of the one specified by the starting time in step 18.

USF on the other lowered numbered PDCHs are not addressing the MS.

28

SS checks that the MS does not send any uplink data block in next block of the message sent in step 27.

29

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCK

USF on PACCH₁ is addressing the MS.

30

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCK

This step is optional; it is performed only if at least 2 timeslots have been assigned in step 18.

USF on PACCH₂ is not addressing the MS. Sent on the same TDMA frame as step 29.

31

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCK

This step is optional; it is performed only if at least 3 timeslots have been assigned in step 18.

USF on PACCH₃ is not addressing the MS, sent on the same TDMA frame as step 29.

32

MS -> SS

UPLINK RLC DATA BLOCK

Received on the assigned PDTCH₁.

33

MS -> SS

UPLINK RLC DATA BLOCK

This step is optional; it is performed only if at least 2 timeslots have been assigned in step 18.

Received on the assigned PDTCH₂ on the same TDMA frame as step 32.

34

MS -> SS

UPLINK RLC DATA BLOCK

This step is optional; it is performed only if at least 3 timeslots have been assigned in step 18.

Received on the assigned PDTCH₃ on the same TDMA frame as step 32.

35

{Completion of uplink RLC data block transfer in extended dynamic mode}

1

{Uplink dynamic allocation two phase access}

N = 1500 octets, without starting time, Assigning the TBF in extended dynamic mode.

Up to 4 timeslots are assigned according to MS multislot class (TS 05.02 Annex B.1) :

• USF₁ on TN₁,
• USF₂ on TN₂,
• USF₃ on TN₃,
• USF₄ on TN₄,

2

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCK

Assigned USF₁ on PACCH₁ addressing the MS. Sent on third block from the last radio block containing the uplink assignment.

3

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCK

USF on PACCH₂ is not addressing the MS, sent on the same TDMA frame as step 2.

4

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCK

This step is optional; it is performed only if 3 timeslots at least have been assigned in step 1.

USF on PACCH₃ is not addressing the MS, sent on the same TDMA frame as step 2.

5

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCK

This step is optional; it is performed only if 4 timeslots have been assigned in step 1.

USF on PACCH₄ is not addressing the MS, sent on the same TDMA frame as step 2.

6

MS -> SS

UPLINK RLC DATA BLOCK

Received on the assigned PDTCH₁.

7

MS -> SS

UPLINK RLC DATA BLOCK

Received on the assigned PDTCH₂ on the same TDMA frame as step 6.

8

MS -> SS

UPLINK RLC DATA BLOCK

This step is optional; it is performed only if 3 timeslots at least have been assigned in step 1.Received on the assigned PDTCH₃ on the same TDMA frame as step 6.

9

MS -> SS

UPLINK RLC DATA BLOCK

This step is optional; it is performed only if 4 timeslots have been assigned in step 1.

Received on the assigned PDTCH₄ on the same TDMA frame as step 6.

10

SS -> MS

PACKET UPLINK ACK/NACK

Assigned USF₁ on PACCH₁ addressing the MS.

11

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCK

USF on PACCH₂ is not addressing the MS, sent on the same TDMA frame as step 10

12

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCK

This step is optional; it is performed only if 3 timeslots at least have been assigned in step 1.

USF on PACCH₃ is not addressing the MS, sent on the same TDMA frame as step 10

13

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCK

This step is optional; it is performed only if 4 timeslots have been assigned in step 1.

USF on PACCH₄ is not addressing the MS, sent on the same TDMA frame as step 10

14

MS -> SS

UPLINK RLC DATA BLOCK

Received on the assigned PDTCH₁.

15

MS -> SS

UPLINK RLC DATA BLOCK

Received on the assigned PDTCH₂ on the same TDMA frame as step 14

16

MS -> SS

UPLINK RLC DATA BLOCK

This step is optional; it is performed only if 3 timeslots at least have been assigned in step 1.

Received on the assigned PDTCH₃ on the same TDMA frame as step 14.

17

MS -> SS

UPLINK RLC DATA BLOCK

This step is optional; it is performed only if 4 timeslots have been assigned in step 1.

Received on the assigned PDTCH₄ on the same TDMA frame as step 14.

18

SS -> MS

PACKET PDCH RELEASE

TIMESLOT_AVAILABLE indicating that the number of slots available is reduced by 1. Highest numbered timeslot assigned in step 1 is released.

19

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCK

Assigned USF addressing the MS. Sent on the PDCH released in step 18. It is sent on the 7^th block from the message sent in step 18.

20

SS checks that the MS does not send any uplink data block in next block of the message sent in step 19.

21

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCK

USF on PACCH₁ is addressing the MS.

22

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCK

This step is optional; it is performed only if at least 2 timeslots are available after PDCH release in step 18.

USF on PACCH₂ is not addressing the MS. Sent on the same TDMA frame as step 21.

23

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCK

This step is optional; it is performed only if at least 3 timeslots are available after PDCH release in step 18.

USF on PACCH₃ is not addressing the MS, sent on the same TDMA frame as step 21.

24

MS -> SS

UPLINK RLC DATA BLOCK

Received on the assigned PDTCH₁.

25

MS -> SS

UPLINK RLC DATA BLOCK

This step is optional; it is performed only if at least 2 timeslots are available after PDCH release in step 18.

Received on the assigned PDTCH₂ on the same TDMA frame as step 24.

26

MS -> SS

UPLINK RLC DATA BLOCK

This step is optional; it is performed only if at least 3 timeslots are available after PDCH release in step 18.

Received on the assigned PDTCH₃ on the same TDMA frame as step 24.

27

{Completion of uplink RLC data block transfer in extended dynamic mode}

1

{Uplink dynamic allocation two phase access}

N = 1500 octets, without starting time, Assigning the TBF in extended dynamic mode.

One slot less (Up to 3 timeslots are assigned) than the allowed limit according to MS multislot class (TS 05.02 Annex B.1):

• USF₂ on TN₂,
• USF₃ on TN₃,
• USF₄ on TN₄,

2

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCK

Assigned USF₂ on PACCH₂ addressing the MS on 3 blocks from the last radio block containing the uplink assignment.

3

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCK

This step is optional; it is performed only if 2 timeslots at least have been assigned in step 1.

USF on PACCH₃ is not addressing the MS, sent on the same TDMA frame as step 2.

4

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCK

This step is optional; it is performed only if 3 timeslots at least have been assigned in step 1.

USF on PACCH₄ is not addressing the MS, sent on the same TDMA frame as step 2.

5

MS -> SS

UPLINK RLC DATA BLOCK

Received on the assigned PDTCH₂.

6

MS -> SS

UPLINK RLC DATA BLOCK

This step is optional; it is performed only if 2 timeslots at least have been assigned in step 1.

Received on the assigned PDTCH₃ on the same TDMA frame as step 5.

7

MS -> SS

UPLINK RLC DATA BLOCK

This step is optional; it is performed only if 3 timeslots at least have been assigned in step 1.

Received on the assigned PDTCH₄ on the same TDMA frame as step 5.

8

SS -> MS

PACKET UPLINK ACK/NACK

Assigned USF₂ on PACCH₂ addressing the MS.

9

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCK

This step is optional; it is performed only if 2 timeslots at least have been assigned in step 1.

USF on PACCH₃ is not addressing the MS, sent on the same TDMA frame as step 8.

10

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCK

This step is optional; it is performed only if 3 timeslots at least have been assigned in step 1.

USF on PACCH₄ is not addressing the MS, sent on the same TDMA frame as step 8.

11

MS -> SS

UPLINK RLC DATA BLOCK

Received on the assigned PDTCH₂.

12

MS -> SS

UPLINK RLC DATA BLOCK

This step is optional; it is performed only if 2 timeslots at least have been assigned in step 1.

Received on the assigned PDTCH₃ on the same TDMA frame as step 11

13

MS -> SS

UPLINK RLC DATA BLOCK

This step is optional; it is performed only if 3 timeslots at least have been assigned in step 1.

Received on the assigned PDTCH₄ on the same TDMA frame as step 11.

14

SS -> MS

PACKET UPLINK ASSIGNMENT

SS reconfigures the TBF. Assignment assigns a starting time of 104 frames. Number of slots is increased by one from the earlier allocation given in step 1.

The slot is assigned at the lower end, i.e. TN₁ is assigned with USF₁ associated with it.

15

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCK

Assigned USF₁ on PACCH₁ addressing the MS. Send on three blocks before the starting time given in step 14.

16

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCK

Assigned USF₂ on PACCH₂ addressing the MS. Send on three blocks before the starting time given in step 14.

17

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCK

This step is optional; it is performed only if 2 timeslots at least have been assigned in step 1.

USF on PACCH₃ is not addressing the MS, sent on the same TDMA frame as step 15.

18

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCK

This step is optional; it is performed only if 3 timeslots at least have been assigned in step 1.

USF on PACCH₄ is not addressing the MS, sent on the same TDMA frame as step 15.

19

SS checks that the MS does not send any data block on PDTCH_1.

20

MS -> SS

UPLINK RLC DATA BLOCK

Received on the assigned PDTCH₂.

21

MS -> SS

UPLINK RLC DATA BLOCK

This step is optional; it is performed only if 2 timeslots at least have been assigned in step 1

Received on the assigned PDTCH₃ on the same TDMA frame as step 20.

22

MS -> SS

UPLINK RLC DATA BLOCK

This step is optional; it is performed only if 3 timeslots at least have been assigned in step 1.

Received on the assigned PDTCH₄ on the same TDMA frame as step 20.

23

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCK

Assigned USF addressing the MS. Sent on the lowest numbered PDCH assigned in step 14. Send on the next block of the block given by starting time in step 14.

USF on the other PDCHs are not addressing the MS.

24

MS -> SS

UPLINK RLC DATA BLOCK

Received on the assigned PDTCH₁.

25

MS -> SS

UPLINK RLC DATA BLOCK

Received on the assigned PDTCH₂ on the same TDMA frame as step 24.

26

MS -> SS

UPLINK RLC DATA BLOCK

This step is optional; it is performed only if 3 timeslots at least have been assigned in step 14.

Received on the assigned PDTCH₃ on the same TDMA frame as step 24.

27

MS -> SS

UPLINK RLC DATA BLOCK

This step is optional; it is performed only if 4 timeslots have been assigned in step 14.

Received on the assigned PDTCH₄ on the same TDMA frame as step 24.

28

{Completion of uplink RLC data block transfer in extended dynamic mode}

1

{Uplink dynamic allocation two phase access}

n = 40 octets, without starting time,

Up to 6 consecutive timeslots are assigned according to MS multislot class (TS 45.002 Annex B.1):

• USF₁ on TN₁,
• USF₂ on TN₂, (USF₂  USF₁)
• up to …
• USF_N on TN_N, where N = 5 or 6.

2

SS -> MS

PACKET DOWNLINK ASSIGNMENT

Sent on the PACCH of PDCH₂, 3 blocks on from the last radio block containing the uplink assignment.

Includes the Polling bit set, and a valid RRBP field.

Includes the TFI assigned to the uplink TBF.

The timeslot assigned is TN₂.

The USF is not addressing the MS.

3

MS-SS

PACKET CONTROL ACKNOWLEDGEMENT

Sent on the PACCH of PDCH₂, and on the radio block specified by the RRBP.

4

{ Completion of uplink RLC data block transfer in extended dynamic mode }

Using all assigned PDTCHs.

1

{Uplink dynamic allocation two phase access}

n = 1500 octets, without starting time,

Up to 6 consecutive timeslots are assigned according to MS multislot class (TS 45.002 Annex B.1):

• USF₁ on TN₁,
• USF₂ on TN₂, (USF₂  USF₁)
• up to …
• USF_N on TN_N, where N = 5 or 6.

2

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCK

Sent on the PACCH of PDCH₃, 3 blocks on from the last radio block containing the uplink assignment; the assigned USF₃ is addressing the MS.

3

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCKS

Sent on the PACCH of PDCH₁, PDCH₂ and PDCH₄ to PDCH_N on the same block period as step 2; the USF is not addressing the MS.

4

MS -> SS

UPLINK RLC DATA BLOCKS

Received on the assigned PDTCH₃ to PDTCH_N

5

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCK

Sent on the PACCH of PDCH₂; the assigned USF₂ is addressing the MS.

6

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCKS

Sent on the PACCH of PDCH₁ and PDCH₃ to PDCH_N on the same block period as step 5; the USF is not addressing the MS.

7

MS -> SS

UPLINK RLC DATA BLOCKS

Received on the assigned PDTCH₂ to PDTCH_N

8

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCK

Sent on the PACCH of PDCH₂; the assigned USF₁ is addressing the MS.

9

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCKS

Sent on the PACCH of PDCH₁ and PDCH₃ to PDCH_N on the same block period as step 8; the USF is not addressing the MS.

10

MS -> SS

UPLINK RLC DATA BLOCKS

Received on all assigned PDTCH₁ to PDTCH_N

11

{ Completion of uplink RLC data block transfer in extended dynamic mode }

Using all assigned PDTCHs.

1

{Uplink dynamic allocation two phase access}

n = 2000 octets, without starting time,

Up to 6 consecutive timeslots are assigned according to MS multislot class (TS 45.002 Annex B.1):

• USF₁ on TN₁,
• USF₂ on TN₂, (USF₂  USF₁)
• up to …
• USF_N on TN_N, where N = 5 or 6.

2

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCKS

Sent on the PACCH of PDCH₁ to PDCH_N, 3 blocks on from the last radio block containing the uplink assignment; the USF values are:

PACCH₁ – USF is not addressing the MS.

PACCH₂ – assigned USF₁ is addressing the MS.

PACCH₃ – USF is not addressing the MS.

up to …

PACCH_N – USF is not addressing the MS.

3

MS -> SS

UPLINK RLC DATA BLOCKS

Received on all assigned PDTCH₁ to PDTCH_N

4

SS -> MS

PACKET PDCH RELEASE

Sent on the PACCH of PDCH₂ on the same block period as step 3; the assigned USF₁ is addressing the MS.

5

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCKS

Sent on the PACCH of PDCH₁ and PDCH₃ to PDCH_N, on the same block period as step 3; the USF values are:

PACCH₁ – USF is not addressing the MS.

PACCH₃ – assigned USF₃ is addressing the MS.

PACCH₄ – USF is not addressing the MS.

up to …

PACCH_N – USF is not addressing the MS.

6

MS -> SS

UPLINK RLC DATA BLOCKS

RLC data blocks may optionally be received on PDTCH₁ and PDTCH_2. RLC data blocks are mandatorily received on assigned PDTCH₃ to PDTCH_N

7

SS -> MS

PACKET DOWNLINK DUMMY CONTROL BLOCK

Sent on the PACCH of PDCH₁ to PDCH_N, on the same block period as step 6; the USF values are:

PACCH₁ – USF is not addressing the MS.

PACCH₂ – assigned USF₁ is addressing the MS.

PACCH₃ – assigned USF₃ is addressing the MS.

PACCH₄ – USF is not addressing the MS.

up to

PACCH_N – USF is not addressing the MS.

8

SS,MS

Steps 6 and 7 are repeated four times more.

9

MS -> SS

UPLINK RLC DATA BLOCKS

RLC data blocks are received on assigned PDTCH₃ to PDTCH_N only.

No RLC data blocks are received on PDTCH₁ and PDTCH₂.

10

{ Completion of uplink RLC data block transfer in extended dynamic mode }

Using PDTCH₃ to PDTCH_N

– TIMESLOTS_AVAILABLE

Indicating that TN₁ and TN₃ to TN_N are available for GPRS. TN₂ is not available.