A.7 Timing and Signalling Characteristics

25.1333GPPRelease 17Requirements for support of radio resource management (FDD)TS

A.7.1 UE Transmit Timing

A.7.1.1 Test Purpose and Environment

The purpose of this test is to verify that the UE initial transmit timing accuracy, maximum amount of timing change in one adjustment, minimum and maximum adjustment rate are within the specified limits. This test will verify the requirements in section 7.1.2.

For this test two cells on the same frequency are used. Table A.7.1 defines the transmitted signal strengths, the relative timing and the propagation condition used for the two cells.

Table A.7.1: Test parameters for UE Transmit Timing requirement

Parameter	Unit	Level
DPCH_Ec/ Ior, Cell 1 and Cell 2	dB	-13.5
CPICH_Ec/ Ior, Cell 1 and Cell 2	dB	-10
PCCPH_Ec/ Ior, Cell 1 and Cell 2	dB	-12
SCH_Ec/ Ior, Cell 1 and Cell 2	dB	-12
PICH_Ec/ Ior, Cell 1 and Cell 2	dB	-15
OCNS_Ec/ Ior, Cell 1 and Cell 2	dB	-1.2
Îor, Cell 1	dBm/3,84 MHz	-96
Îor, Cell 2	dBm/3,84 MHz	-99
Information data rate	kbps	12.2
Relative delay of path received from cell 2 with respect to cell 1	μs	+/-2
Propagation condition	AWGN

A.7.1.2 Test Requirements

For parameters specified in Table A.7.1, the UE initial transmit timing accuracy, the maximum amount of timing change in one adjustment, the minimum and the maximum adjustment rate shall be within the limits defined in section 7.1.2.

The relevant soft handover parameters shall be set such that the UE enters soft handover with cell 1 and
cell 2 when both cells are sending a signal. The following sequence of events shall be used to verify that the requirements are met.

a) After a connection is set up with cell 1, the test system shall verify that the UE transmit timing offset is within T₀ +/- 1.5 chips with respect to the first detected received path (in time) of the downlink DPCCH/DPDCH of cell 1. T₀ is defined in TS 25.211[2].

b) Test system introduces cell 2 into the test system at delay +2 μs from cell 1.

c) Test system verifies that cell 2 is added to the active set.

d) Test system shall verify that the UE transmit timing offset is still within T₀ +/- 1.5 chips with respect to the first detected path (in time) of the downlink DPCCH/DPDCH of cell 1.

e) Test system switches Tx timing of cell 2 to a delay of -2 μs with respect to cell 1.

f) Test system verifies cell 2 remains in the active set.

g) Test system shall verify that the UE transmit timing offset is still within T₀ +/- 1.5 chips with respect to the first detected path (in time) of the downlink DPCCH/DPDCH of cell 1.

h) Test system stops sending cell 1 signals.

i) Test system verifies that UE transmit timing adjustment starts no later than the time when the whole active set update message is available at the UE taking the RRC procedure delay into account. The adjustment step size and the adjustment rate shall be according to the requirements in section 7.1.2 until the UE transmit timing offset is within T₀ +/- 1.5 chips with respect to the first detected path (in time) of the downlink DPCCH/DPDCH of cell 2.

j) Test system shall verify that the UE transmit timing offset stays within T₀ +/- 1.5 chips with respect to the first detected path (in time) of the downlink DPCCH/DPDCH of cell 2.

k) Test system starts sending cell 1 signal again with its original timing.

l) Test system verifies that cell 1 is added to the active set.

m) Test system verifies that the UE transmit timing is still within T₀ +/- 1.5chips with respect to the first detected path (in time) of the downlink DPCCH/DPDCH of cell 2.

n) Test system stops sending cell 2 signals.

o) Test system verifies that UE transmit timing adjustment starts no later than the time when the whole active set update message is available at the UE taking the RRC procedure delay into account. The adjustment step size and the adjustment rate shall be according to the requirements in section 7.1.2 until the UE transmit timing offset is within T₀ +/- 1.5 chips with respect to the first detected path (in time) of the downlink DPCCH/DPDCH of cell 1.

p) Test system shall verify that the UE transmit timing offset stays within T₀ +/- 1.5 chips with respect to the first detected path (in time) of the downlink DPCCH/DPDCH of cell 1.