4.3A Mapping of DL FET ACK/NACK bits

25.2123GPPMultiplexing and channel coding (FDD)Release 17TS

Tools: ARFCN - Frequency Conversion for 5G NR/LTE/UMTS/GSM

When slot format 5 is used for uplink DPCCH, TFCI fields in each 20ms TTI contain DL FET ACK/NACK indicators in all transmitted slots that do not contain TFCI bits (see subclauses 4.3.5.1A and 4.3.5.2.1.2). Each DL FET ACK/NACK indicator is encoded as specified in Table 9. When DL_DCH_FET_Config = 0, the bits that replace DL FET ACK/NACK indicators are unspecified.

Table 9: ACK/NACK transmission on uplink DPCCH

DL FET ACK/NACK indicator	bits in slot i
ACK	1
NACK	0

Let the slots in a 20ms CI be numbered 0,1,…29. For each i =0,1,…29, if slot i is not in a compressed-mode gap and does not contain TFCI bits, then a DL FET NACK indicator is transmitted in slot i if at least one of the following conditions holds:

a) At least one of the transport blocks transmitted on downlink DPDCH with a TTI that includes slot i has not been successfully decoded by the UE.

b) i belongs in the set S={11, 13, 15, 17, 19, 21, 23, 25, 27, 29}, and a DL FET ACK indication has not been sent in any prior slot j,0 ≤ j < i, in this 20ms TTI.

c) A downlink slot containing bits of a non-zero transport block of a maximum TTI TrCH overlaps with slot i.

A DL FET ACK indicator is sent in all transmitted UL DPCCH slots that do not fall in a compressed mode gap and do not contain a DL FET NACK indicator or TFCI bit. If a 20ms CI contains a DL FET ACK indication, it always contains at least two slots carrying a DL FET ACK indication.