5.2 Uplink physical channels
25.2113GPPPhysical channels and mapping of transport channels onto physical channels (FDD)Release 17TS
5.2.1 Dedicated uplink physical channels
There are seven types of uplink dedicated physical channels, the uplink Dedicated Physical Data Channel (uplink DPDCH), the uplink Dedicated Physical Control Channel (uplink DPCCH), the uplink Secondary Dedicated Physical Control Channel (uplink S-DPCCH), the uplink Dedicated Physical Control Channel 2 (uplink DPCCH2), the uplink E-DCH Dedicated Physical Data Channel (uplink E-DPDCH), the uplink E-DCH Dedicated Physical Control Channel (uplink E-DPCCH) and the uplink Dedicated Control Channel associated with HS-DSCH transmission (uplink HS-DPCCH).
The DPDCH, the DPCCH, the DPCCH2, the S-DPCCH, the E-DPDCH, the E-DPCCH and the HS-DPCCH are I/Q code multiplexed (see [4]).
5.2.1.1 DPCCH, DPCCH2, S-DPCCH and DPDCH
The uplink DPDCH is used to carry the DCH transport channel. There may be zero, one, or several uplink DPDCHs on each radio link.
The uplink DPCCH is used to carry control information generated at Layer 1. The Layer 1 control information consists of known pilot bits to support channel estimation for coherent detection, transmit power-control (TPC) commands, feedback information (FBI), and an optional transport-format combination indicator (TFCI). The transport-format combination indicator informs the receiver about the instantaneous transport format combination of the transport channels mapped to the simultaneously transmitted uplink DPDCH radio frame. There is one and only one uplink DPCCH on each radio link. The uplink DPCCH may also carry DL FET ACK/NACK signalling information for DL FET operation when DL_DCH_FET_Config = 1.
The uplink DPCCH2 is used to carry control information generated at Layer 1. The Layer 1 control information consists of known pilot bits to support channel estimation for coherent detection, and transmit power-control (TPC) commands. When DPCCH2 is configured there is one and only one uplink DPCCH2 for all radio links. When DPCCH2 is configured, the UE shall transmit DPCCH2 only in the slots in which DPCCH is transmitted.
The uplink S-DPCCH is used to carry control information generated at Layer 1. The Layer 1 control information consists of known pilot bits to support channel sounding and channel estimation for coherent detection. There is up to one uplink S-DPCCH on each radio link in the case that UL_CLTD_Enabled as defined in [5] is TRUE. Figure 1 shows the frame structure of the uplink DPDCH, the uplink DPCCH, the uplink DPCCH2 and the uplink S-DPCCH. Each radio frame of length 10 ms is split into 5 subframes, each of 3 slots, each of length Tslot = 2560 chips, corresponding to one power-control period. The DPDCH, DPCCH, S-DPCCH and DPCCH2 are always frame aligned with each other.
Figure 1: Frame structure for uplink DPDCH/DPCCH/S-DPCCH/DPCCH2
The parameter k in figure 1 determines the number of bits per uplink DPDCH slot. It is related to the spreading factor SF of the DPDCH as SF = 256/2k. The DPDCH spreading factor may range from 256 down to 4. The spreading factor of the uplink DPCCH, the uplink DPCCH2 and the uplink S-DPCCH is always equal to 256, i.e. there are 10 bits per uplink DPCCH/S-DPCCH/DPCCH2 slot.
The exact number of bits of the uplink DPDCH and the different uplink DPCCH fields (Npilot, NTFCI, NFBI, and NTPC) is given by table 1 and table 2. What slot format to use is configured by higher layers and can also be reconfigured by higher layers. The exact number of bits of the uplink S-DPCCH is given by table 2A.
The uplink DPCCH2 reuses slot format #1 of DPCCH, and the exact number of bits is given in table 2.
The channel bit and symbol rates given in table 1, table 2 and table 2A are the rates immediately before spreading. The pilot patterns are given in table 3 and table 4, the TPC bit pattern is given in table 5.
The FBI bits are used to support techniques requiring feedback from the UE to the UTRAN Access Point for operation of closed loop mode transmit diversity. The use of the FBI bits is described in detail in [5].
Table 1: DPDCH fields
|
Slot Format #i |
Channel Bit Rate (kbps) |
Channel Symbol Rate (ksps) |
SF |
Bits/ Frame |
Bits/ Slot |
Ndata |
|
0 |
15 |
15 |
256 |
150 |
10 |
10 |
|
1 |
30 |
30 |
128 |
300 |
20 |
20 |
|
2 |
60 |
60 |
64 |
600 |
40 |
40 |
|
3 |
120 |
120 |
32 |
1200 |
80 |
80 |
|
4 |
240 |
240 |
16 |
2400 |
160 |
160 |
|
5 |
480 |
480 |
8 |
4800 |
320 |
320 |
|
6 |
960 |
960 |
4 |
9600 |
640 |
640 |
There are two types of uplink dedicated physical channels; those that include TFCI (e.g. for several simultaneous services) and those that do not include TFCI (e.g. for fixed-rate services). These types are reflected by the duplicated rows of table 2. It is the UTRAN that determines if a TFCI should be transmitted and it is mandatory for all UEs to support the use of TFCI in the uplink. The mapping of TFCI bits onto slots is described in [3].
DPCCH slot format 5 is used when DL_DCH_FET_Config is configured by higher layers. In this case, over a 20ms Compression Interval (CI) consisting of 30 slots, the bits in the TFCI field carry TFCI information in the first 10 slots, and may carry an ACK/NACK indicator for DL FET in the remaining 20 slots. The ACK/NACK for DL FET is sent when DL_DCH_FET_Config = 1.
In compressed mode, DPCCH slot formats with TFCI fields are changed. There are two possible compressed slot formats for normal slot formats 0 and 2. They are labelled A and B and the selection between them is dependent on the number of slots that are transmitted in each frame in compressed mode. When DL_DCH_FET_Config is configured by higher layers, UL DPCCH slot format 5 is used in compressed mode. In compressed mode when UL_DCH_FET_Config is configured by higher layers, TFCI bits represent TFCI information in the first 10 slots that are not in compressed-mode gaps in a 20ms CI. The TFCI bits in subsequent slots that are not in the compressed mode gaps represent ACK/NACK indication for DL FET when DL_DCH_FET_Config = 1.
If UL_DTX_Active is TRUE (see [5]), the number of transmitted slots per radio frame may be less than the number shown in Table 2 and Table 2A.
Table 2: DPCCH fields
|
Slot Format #i |
Channel Bit Rate (kbps) |
Channel Symbol Rate (ksps) |
SF |
Bits/ Frame |
Bits/ Slot |
Npilot |
NTPC |
NTFCI |
NFBI |
Transmitted slots per radio frame |
|
0 |
15 |
15 |
256 |
150 |
10 |
6 |
2 |
2 |
0 |
15 |
|
0A |
15 |
15 |
256 |
150 |
10 |
5 |
2 |
3 |
0 |
10-14 |
|
0B |
15 |
15 |
256 |
150 |
10 |
4 |
2 |
4 |
0 |
8-9 |
|
1 |
15 |
15 |
256 |
150 |
10 |
8 |
2 |
0 |
0 |
8-15 |
|
2 |
15 |
15 |
256 |
150 |
10 |
5 |
2 |
2 |
1 |
15 |
|
2A |
15 |
15 |
256 |
150 |
10 |
4 |
2 |
3 |
1 |
10-14 |
|
2B |
15 |
15 |
256 |
150 |
10 |
3 |
2 |
4 |
1 |
8-9 |
|
3 |
15 |
15 |
256 |
150 |
10 |
7 |
2 |
0 |
1 |
8-15 |
|
4 |
15 |
15 |
256 |
150 |
10 |
6 |
4 |
0 |
0 |
8-15 |
|
5 |
15 |
15 |
256 |
150 |
10 |
6 |
2 |
2* |
0 |
8-15 |
* NOTE: In a 20ms CI of 30 slots, TFCI bits represent TFCI information in the first 10 slots and may represent DL FET ACK/NACK indication for DL FET in the remaining slots. Slot format 5 is also used in compressed mode for UL DPCCH.
Table 2A: S-DPCCH fields
|
Slot Format #i |
Channel Bit Rate (kbps) |
Channel Symbol Rate (ksps) |
SF |
Bits/ Frame |
Bits/ Slot |
Npilot |
Nfixed |
Transmitted slots per radio frame |
|
1 |
15 |
15 |
256 |
150 |
10 |
8 |
2 |
8-15 |
The pilot bit pattern for S-DPCCH is the same as that for uplink DPCCH with Npilot = 8. The Nfixed bits in the S-DPCCH are fixed to "10".
The pilot bit pattern for DPCCH2 is the same as that for uplink DPCCH with Npilot = 8.
The pilot bit patterns are described in table 3 and table 4. The shadowed column part of pilot bit pattern is defined as FSW and FSWs can be used to confirm frame synchronization. (The value of the pilot bit pattern other than FSWs shall be "1".)
Table 3: Pilot bit patterns for uplink DPCCH with Npilot = 3, 4, 5 and 6
|
Npilot = 3 |
Npilot = 4 |
Npilot = 5 |
Npilot = 6 |
|||||||||||||||
|
Bit # |
0 |
1 |
2 |
0 |
1 |
2 |
3 |
0 |
1 |
2 |
3 |
4 |
0 |
1 |
2 |
3 |
4 |
5 |
|
Slot #0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 |
1 0 0 0 1 1 1 1 0 1 0 1 1 0 0 |
1 0 1 0 0 1 1 0 1 1 1 0 0 0 0 |
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 |
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 |
1 0 0 0 1 1 1 1 0 1 0 1 1 0 0 |
1 0 1 0 0 1 1 0 1 1 1 0 0 0 0 |
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 |
1 0 0 0 1 1 1 1 0 1 0 1 1 0 0 |
1 0 1 0 0 1 1 0 1 1 1 0 0 0 0 |
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 |
1 1 0 0 0 1 0 0 1 1 0 1 0 1 1 |
0 0 1 0 1 0 0 0 0 1 1 1 0 1 1 |
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 |
1 0 0 0 1 1 1 1 0 1 0 1 1 0 0 |
1 0 1 0 0 1 1 0 1 1 1 0 0 0 0 |
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 |
1 1 0 0 0 1 0 0 1 1 0 1 0 1 1 |
0 0 1 0 1 0 0 0 0 1 1 1 0 1 1 |
Table 4: Pilot bit patterns for uplink DPCCH with Npilot = 7 and 8
|
Npilot = 7 |
Npilot = 8 |
||||||||||||||
|
Bit # |
0 |
1 |
2 |
3 |
4 |
5 |
6 |
0 |
1 |
2 |
3 |
4 |
5 |
6 |
7 |
|
Slot #0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 |
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 |
1 0 0 0 1 1 1 1 0 1 0 1 1 0 0 |
1 0 1 0 0 1 1 0 1 1 1 0 0 0 0 |
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 |
1 1 0 0 0 1 0 0 1 1 0 1 0 1 1 |
0 0 1 0 1 0 0 0 0 1 1 1 0 1 1 |
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 |
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 |
1 0 0 0 1 1 1 1 0 1 0 1 1 0 0 |
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 |
1 0 1 0 0 1 1 0 1 1 1 0 0 0 0 |
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 |
1 1 0 0 0 1 0 0 1 1 0 1 0 1 1 |
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 |
0 0 1 0 1 0 0 0 0 1 1 1 0 1 1 |
The relationship between the TPC bit pattern and transmitter power control command is presented in table 5.
Table 5: TPC Bit Pattern
|
TPC Bit Pattern |
Transmitter power control command |
|
|
NTPC = 2 |
NTPC = 4 |
|
|
11 00 |
1111 0000 |
1 0 |
Multi-code operation is possible for the uplink dedicated physical channels. When multi-code transmission is used, several parallel DPDCH are transmitted using different channelization codes, see [4]. However, there is only one DPCCH per radio link, one DPCCH2 if DPCCH2 is configured and up to one S-DPCCH in the case that UL_CLTD_Enable is TRUE.
A period of uplink DPCCH transmission prior to the start of the uplink DPDCH transmission (uplink DPCCH power control preamble) shall be used for initialisation of a DCH. The length of the power control preamble is a higher layer parameter, Npcp , signalled by the network [5]. The UL DPCCH shall take the same slot format in the power control preamble as afterwards, as given in table 2. When Npcp > 0 the pilot patterns of table 3 and table 4 shall be used. The timing of the power control preamble is described in [5], subclause 4.3.2.3. The TFCI field is filled with "0" bits.
5.2.1.2 HS-DPCCH
Figure 2A illustrates the frame structure of the HS-DPCCH. The HS-DPCCH carries uplink feedback signalling related to downlink HS-DSCH transmission and to HS-SCCH orders according to subclause 6A.1.1 in [5]. The feedback signalling consists of Hybrid-ARQ Acknowledgement (HARQ-ACK) and Channel-Quality Indication (CQI), in case the UE is configured in MIMO mode or in MIMO mode with four transmit antennas Precoding Control Indication (PCI) as well and in case the UE is configured in MIMO mode with four transmit antennas the number of transport blocks preferred (NTBP) as well [3]. Each sub frame of length 2 ms (3*2560 chips) consists of 3 slots, each of length 2560 chips. The HARQ-ACK is carried in the first slot of the HS-DPCCH sub-frame. The CQI, in case the UE is configured in MIMO mode also the PCI, and in case the UE is configured in MIMO mode with four transmit antennas also the PCI and the number of UE preferred transport blocks are carried in the second and third slot of a HS-DPCCH sub-frame. There is at most one HS-DPCCH on each radio link if Secondary_Cell_Enabled as defined in [5] is less than 4 in case the UE is not configured in MIMO mode with four transmit antennas, 2 in case the UE is configured in MIMO mode with four transmit antennas and at most two HS-DPCCHs otherwise. If DPCCH2 is not configured, the HS-DPCCH(s) can only exist together with an uplink DPCCH. If DPCCH2 is configured, the HS-DPCCH(s) can only exist together with an uplink DPCCH2. The timing of the HS-DPCCH relative to the uplink DPCCH is shown in section 7.7 for the case where one HS-DPCCH exists. In the case where two HS-DPCCH exist, both HS-DPCCHs have identical timing.
Figure 2A: Frame structure for uplink HS-DPCCH
The slot formats for uplink HS-DPCCH are defined in Table 5A.
Table 5A: HS-DPCCH fields
|
Slot Format #i |
Channel Bit Rate (kbps) |
Channel Symbol Rate (ksps) |
SF |
Bits/ Subframe |
Bits/ Slot |
Transmitted slots per Subframe |
|
0 |
15 |
15 |
256 |
30 |
10 |
3 |
|
1 |
30 |
30 |
128 |
60 |
20 |
3 |
5.2.1.3 E-DPCCH and E-DPDCH
The E-DPDCH is used to carry the E-DCH transport channel. There may be zero, one, or several E-DPDCH on each radio link.
The E-DPCCH is a physical channel used to transmit control information associated with the E-DCH. There is at most one E-DPCCH on each radio link.
E-DPDCH and E-DPCCH are always transmitted simultaneously, except for the following cases when E-DPCCH is transmitted without E-DPDCH:
– when E-DPDCH but not E-DPCCH is DTXed due to power scaling as described in [5] section 5.1.2.6, or
– during the ndtx E‑DPDCH idle slots if nmax>ntx1 as described in [3] section 4.4.5.2.
E-DPCCH shall not be transmitted in a slot unless DPCCH is also transmitted in the same slot.
Figure 2B shows the E-DPDCH and E-DPCCH (sub)frame structure. Each radio frame is divided in 5 subframes, each of length 2 ms; the first subframe starts at the start of each radio frame and the 5th subframe ends at the end of each radio frame.
An E-DPDCH may use BPSK, 4PAM or 8PAM modulation symbols. In figure 2B, M is the number of bits per modulation symbol i.e. M=1 for BPSK, M=2 for 4PAM and M=3 for 8PAM.
The E-DPDCH slot formats, corresponding rates and number of bits are specified in Table 5B. The E-DPCCH slot format is listed in Table 5C.
Figure 2B: E-DPDCH frame structure
Table 5B: E-DPDCH slot formats
|
Slot Format #i |
Channel Bit Rate (kbps) |
Bits/Symbol M |
SF |
Bits/ Frame |
Bits/ Subframe |
Bits/Slot Ndata |
|
0 |
15 |
1 |
256 |
150 |
30 |
10 |
|
1 |
30 |
1 |
128 |
300 |
60 |
20 |
|
2 |
60 |
1 |
64 |
600 |
120 |
40 |
|
3 |
120 |
1 |
32 |
1200 |
240 |
80 |
|
4 |
240 |
1 |
16 |
2400 |
480 |
160 |
|
5 |
480 |
1 |
8 |
4800 |
960 |
320 |
|
6 |
960 |
1 |
4 |
9600 |
1920 |
640 |
|
7 |
1920 |
1 |
2 |
19200 |
3840 |
1280 |
|
8 |
1920 |
2 |
4 |
19200 |
3840 |
1280 |
|
9 |
3840 |
2 |
2 |
38400 |
7680 |
2560 |
|
10 |
2880 |
3 |
4 |
28800 |
5760 |
1920 |
|
11 |
5760 |
3 |
2 |
57600 |
11520 |
3840 |
Table 5C: E-DPCCH slot formats
|
Slot Format #i |
Channel Bit Rate (kbps) |
SF |
Bits/ Frame |
Bits/ Subframe |
Bits/Slot Ndata |
|
0 |
15 |
256 |
150 |
30 |
10 |
5.2.1.3A S-E-DPCCH and S-E-DPDCH
The S-E-DPDCH is used to carry the E-DCH transport channel. When UL_MIMO_Enabled is set to TRUE and rank-2 transmission takes place on a radio link, the number of S-E-DPDCH channels on that radio link is 4, otherwise, it is zero.
The S-E-DPCCH is a physical channel used to transmit control information associated with the S-E-DPDCH. There is at most one S-E-DPCCH on each radio link.
S-E-DPDCH and S-E-DPCCH are always transmitted simultaneously.
S-E-DPCCH shall not be transmitted in a slot unless DPCCH and S-DPCCH is also transmitted in the same slot.
The S-E-DPDCH frame structure is the same as the E-DPDCH frame structure. The S-E-DPCCH frame structure is the same as the E-DPCCH frame structure.
An S-E-DPDCH may use BPSK, 4PAM or 8PAM modulation symbols.
The S-E-DPDCH slot formats, corresponding rates and number of bits are as specified for slot formats 6-11 in table 5B for E-DPDCH. Slot formats 0-5 are not applicable for S-E-DPDCH.
The S-E-DPCCH slot format is as specified for E-DPCCH in Table 5C.
5.2.2 Common uplink physical channels
5.2.2.1 Physical Random Access Channel (PRACH)
The Physical Random Access Channel (PRACH) is used to carry the RACH.
5.2.2.1.1 Overall structure of random-access transmission
The random-access transmission is based on a Slotted ALOHA approach with fast acquisition indication. The UE can start the random-access transmission at the beginning of a number of well-defined time intervals, denoted access slots. There are 15 access slots per two frames and they are spaced 5120 chips apart, see figure 3. The timing of the access slots and the acquisition indication is described in subclause 7.3. Information on what access slots are available for random-access transmission is given by higher layers.
Figure 3: RACH access slot numbers and their spacing
The structure of the random-access transmission is shown in figure 4. The random-access transmission consists of one or several preambles of length 4096 chips and a message of length 10 ms or 20 ms.
Figure 4: Structure of the random-access transmission
5.2.2.1.2 RACH preamble part
Each preamble is of length 4096 chips and consists of 256 repetitions of a signature of length 16 chips. There are a maximum of 16 available signatures, see [4] for more details.
5.2.2.1.3 RACH message part
Figure 5 shows the structure of the random-access message part radio frame. The 10 ms message part radio frame is split into 15 slots, each of length Tslot = 2560 chips. Each slot consists of two parts, a data part to which the RACH transport channel is mapped and a control part that carries Layer 1 control information. The data and control parts are transmitted in parallel. A 10 ms message part consists of one message part radio frame, while a 20 ms message part consists of two consecutive 10 ms message part radio frames. The message part length is equal to the Transmission Time Interval of the RACH Transport channel in use. This TTI length is configured by higher layers.
The data part consists of 10*2k bits, where k=0,1,2,3. This corresponds to a spreading factor of 256, 128, 64, and 32 respectively for the message data part.
The control part consists of 8 known pilot bits to support channel estimation for coherent detection and 2 TFCI bits. This corresponds to a spreading factor of 256 for the message control part. The pilot bit pattern is described in table 8. The total number of TFCI bits in the random-access message is 15*2 = 30. The TFCI of a radio frame indicates the transport format of the RACH transport channel mapped to the simultaneously transmitted message part radio frame. In case of a 20 ms PRACH message part, the TFCI is repeated in the second radio frame.
Figure 5: Structure of the random-access message part radio frame
Table 6: Random-access message data fields
|
Slot Format #i |
Channel Bit Rate (kbps) |
Channel Symbol Rate (ksps) |
SF |
Bits/ Frame |
Bits/ Slot |
Ndata |
|
0 |
15 |
15 |
256 |
150 |
10 |
10 |
|
1 |
30 |
30 |
128 |
300 |
20 |
20 |
|
2 |
60 |
60 |
64 |
600 |
40 |
40 |
|
3 |
120 |
120 |
32 |
1200 |
80 |
80 |
Table 7: Random-access message control fields
|
Slot Format #i |
Channel Bit Rate (kbps) |
Channel Symbol Rate (ksps) |
SF |
Bits/ Frame |
Bits/ Slot |
Npilot |
NTFCI |
|
0 |
15 |
15 |
256 |
150 |
10 |
8 |
2 |
Table 8: Pilot bit patterns for RACH message part with Npilot = 8
|
Npilot = 8 |
||||||||
|
Bit # |
0 |
1 |
2 |
3 |
4 |
5 |
6 |
7 |
|
Slot #0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 |
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 |
1 0 0 0 1 1 1 1 0 1 0 1 1 0 0 |
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 |
1 0 1 0 0 1 1 0 1 1 1 0 0 0 0 |
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 |
1 1 0 0 0 1 0 0 1 1 0 1 0 1 1 |
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 |
0 0 1 0 1 0 0 0 0 1 1 1 0 1 1 |