6.1 General

25.1413GPPBase Station (BS) conformance testing (FDD)Release 17TS

Unless otherwise stated, the requirements in clause 6 are expressed for a single transmitter antenna connector. In case of transmit diversity, DB-DC-HSDPA or MIMO transmission, the requirements apply for each transmitter antenna connector.

A BS supporting DC-HSDPA and DB-DC-HSDPA transmits two cells simultaneously. A BS supporting DC-HSDPA transmits two cells simultaneously on adjacent carrier frequencies.

Unless otherwise stated, all tests in this clause shall be performed at the BS antenna connector (test port A) with a full complement of transceivers for the configuration in normal operating conditions. If any external apparatus such as a TX amplifier, a filter or the combination of such devices is used, the tests according to clauses 4.6.2 and/or 4.6.4, depending on the device added, shall be performed to ensure that the requirements are met at test port B.

Figure 6.1: Transmitter test ports

Power levels are expressed in dBm.

6.1.1 Test Models

The set-up of physical channels for transmitter tests shall be according to one of the Test Models below. A reference to the applicable table is made with each test.

For Tx diversity transmission, the same Test Model shall be used for both antennas. No diversity coding of the Test Models is required.

A code "level setting" of -X dB is the setting that according to the base station manufacturer will result in a code domain power of nominally X dB below the maximum output power. The relative accuracy of the code domain power to the maximum output power shall have tolerance of ±1 dB.

6.1.1.1 Test Model 1 – TM1

This model shall be used for tests on:

– occupied bandwidth;

– spectrum emission mask;

– ACLR;

– spurious emissions;

– transmit intermodulation;

– base station maximum output power.

– Total power dynamic range (at Pmax,c)

– Home base station output power for adjacent channel protection

– Frequency error (at Pmax,c)

– IPDL time mask

Due to the amplitude statistics of TM1 [2], it is sufficient to test all requirements above with TM1 regardless of the modulation schemes supported by the Node-B.

In addition, the test model is used for Error Vector Magnitude using QPSK modulation (at Pmax,c).

64 DPCHs at 30 ksps (SF=128) are distributed randomly across the code space, at random power levels and random timing offsets are defined so as to simulate a realistic traffic scenario which may have high PAR (Peak to Average Ratio).

Considering that not every base station implementation will support 64 DPCH, variants of this test model containing 32 and 16 DPCH are also specified. For Home base station, additional options of this test model containing 8 and 4 DPCH are also specified. The conformance test shall be performed using the largest of these options that can be supported by the equipment under test.

"Fraction of power" is relative to the maximum output power on the TX antenna interface under test.

Table 6.1: TM1 Active Channels

Type

Number of Channels

Fraction of

Power (%)

Level setting ( dB)

Channelization Code

Timing offset (x256Tchip)

P-CCPCH+SCH

1

10

-10

1

0

Primary CPICH

1

10

-10

0

0

PICH

1

1.6

-18

16

120

S-CCPCH containing PCH (SF=256)

1

1.6

-18

3

0

DPCH

(SF=128)

4*/8*/16/32/64

76.8 in total

see table 6.2

see table 6.2

see table 6.2

Note *: Only applicable to Home BS

Table 6.2: DPCH Spreading Code, Timing offsets and level settings for TM1

Code

Timing offset (x256Tchip)

Level settings

( dB) (4 codes)*

Level settings

( dB) (8 codes)*

Level settings

( dB) (16 codes)

Level settings

( dB) (32 codes)

Level settings

( dB) (64 codes)

2

86

-5

-7

-10

-13

-16

11

134

-16

-12

-13

-16

17

52

-12

-14

-16

23

45

-14

-15

-17

31

143

-11

-17

-18

38

112

-7

-11

-13

-14

-20

47

59

-17

-16

-16

55

23

-11

-16

-18

-17

62

1

-13

-16

-16

69

88

-15

-19

-19

78

30

-9

-10

-14

-17

-22

85

18

-12

-18

-15

-20

94

30

-19

-17

-16

102

61

-17

-22

-17

113

128

-8

-15

-20

-19

119

143

-9

-12

-9

-24

-21

7

83

-20

-19

13

25

-18

-21

20

103

-14

-18

27

97

-14

-20

35

56

-16

-24

41

104

-19

-24

51

51

-18

-22

58

26

-17

-21

64

137

-22

-18

74

65

-19

-20

82

37

-19

-17

88

125

-16

-18

97

149

-18

-19

108

123

-15

-23

117

83

-17

-22

125

5

-12

-21

4

91

-17

9

7

-18

12

32

-20

14

21

-17

19

29

-19

22

59

-21

26

22

-19

28

138

-23

34

31

-22

36

17

-19

40

9

-24

44

69

-23

49

49

-22

53

20

-19

56

57

-22

61

121

-21

63

127

-18

66

114

-19

71

100

-22

76

76

-21

80

141

-19

84

82

-21

87

64

-19

91

149

-21

95

87

-20

99

98

-25

105

46

-25

110

37

-25

116

87

-24

118

149

-22

122

85

-20

126

69

-15

Note *: Only applicable to Home BS

6.1.1.2 Test Model 2 – TM2

This model shall be used for tests on:

– output power dynamics.

– CPICH power accuracy.

Table 6.3: TM2 Active Channels

Type

Number of Channels

Fraction of

Power (%)

Level setting ( dB)

Channelization Code

Timing offset (x256Tchip)

P-CCPCH+SCH

1

10

-10

1

0

Primary CPICH

1

10

-10

0

0

PICH

1

5

-13

16

120

S-CCPCH containing PCH (SF=256)

1

5

-13

3

0

DPCH

(SF=128)

3

2 x 10,1 x 50

2 x -10, 1 x -3

24, 72,

120

1, 7,

2

6.1.1.3 Test Model 3 – TM3

This model shall be used for tests on:

– peak code domain error.

Table 6.4: TM3 Active Channels

Type

Number of Channels

Fraction of

Power (%)

4*/8*/16/32

Level settings ( dB)

4*/8*/16/32

Channelization Code

Timing offset (x256Tchip)

P-CCPCH+SCH

1

15,8/15,8/12,6/7,9

-8/ -8 / -9 / -11

1

0

Primary CPICH

1

15.8/15.8/12,6/7,9

-8 / -8 / -9 / -11

0

0

PICH

1

2.5/2.5/5/1.6

-16/-16/-13/-18

16

120

S-CCPCH containing PCH (SF=256)

1

2.5/2.5/5/1.6

-16/-16/-13/-18

3

0

DPCH

(SF=256)

4*/8*/16/32

63,4/63,4/63,7/80,4 in total

see table 6.5

see table 6.5

see table 6.5

Note *: Only applicable to Home BS

As with TM1, not every base station implementation will support 32 DPCH, a variant of this test model containing 16 DPCH are also specified. For Home base station, additional options of this test model containing 8 and 4 DPCH are also specified. The conformance test shall be performed using the larger of these options that can be supported by the equipment under test.

Table 6.5: DPCH Spreading Code, Toffset and Power for TM3

Code

Toffset

Level settings

( dB) (4 codes)*

Level settings

( dB) (8 codes)*

Level settings

( dB) (16 codes)

Level settings

( dB) (32 codes)

64

86

-8

-11

-14

-16

69

134

-14

-16

74

52

-11

-14

-16

78

45

-14

-16

83

143

-14

-16

89

112

-8

-11

-14

-16

93

59

-14

-16

96

23

-11

-14

-16

100

1

-14

-16

105

88

-14

-16

109

30

-8

-11

-14

-16

111

18

-11

-14

-16

115

30

-14

-16

118

61

-14

-16

122

128

-11

-14

-16

125

143

-8

-11

-14

-16

67

83

-16

71

25

-16

76

103

-16

81

97

-16

86

56

-16

90

104

-16

95

51

-16

98

26

-16

103

137

-16

108

65

-16

110

37

-16

112

125

-16

117

149

-16

119

123

-16

123

83

-16

126

5

-16

Note *: Only applicable to Home BS

6.1.1.4 Test Model 4 – TM4

This model shall be used for tests on:

– EVM measurement

– Total power dynamic range

– Frequency error

Table 6.6: TM4 Active Channels

Type

Number of Channels

Fraction of

Power (%)

Level setting ( dB)

Channelization Code

Timing offset

PCCPCH+SCH when Primary CPICH is disabled

1

-X

1

0

PCCPCH+SCH when Primary CPICH is enabled

1

-X-3

1

0

Primary CPICH1

1

-X-3

0

0

Note 1: The CPICH channel is optional.

6.1.1.4A Test Model 5 – TM5

This model shall be used for tests on:

– EVM for base stations supporting HS-PDSCH transmission using 16QAM modulation (at Pmax,c)

Considering that not every base station implementation will support 8 HS-PDSCH + 30 DPCH, variants of this test model containing 4 HS-PDSCH + 14 DPCH and 2 HS-PDSCH + 6 DPCH are also specified. For Home base station, an additional option of this test model containing 4 HS-PDSCH + 4 DPCH is also specified. The conformance test shall be performed using the largest of these options that can be supported by the equipment under test, where the largest is firstly determined by the number of HS-PDSCH and then by the number of DPCH.

Each HS-PDSCH is modulated by 16QAM.

Table 6.6A: TM5 Active Channels

Type

Number of Channels

Fraction of

Power (%)

Level setting ( dB)

Channelization Code

Timing offset (x256Tchip)

P-CCPCH+SCH

1

7.9

-11

1

0

Primary CPICH

1

7.9

-11

0

0

PICH

1

1.3

-19

16

120

S-CCPCH containing PCH (SF=256)

1

1.3

-19

3

0

DPCH

(SF=128)

30/14/6/4(*)

14/14.2/14.4/14.2 in total

see table 6.6.B

see table 6.6B

see table 6.6.B

HS-SCCH

2

4 in total

see table 6.6C

see table 6.6C

see table 6.6C

HS-PDSCH (16QAM)

8/4/2(*)

63.6/63.4/63.2 in total

see table 6.6D

see table 6.6D

see table 6.6D

Note *: 2 HS-PDSCH shall be taken together with 6 DPCH, 4 HS-PDSCH shall be taken with 14 DPCH or (for Home BS only) 4 DPCH, and 8 HS-PDSCH shall be taken together with 30 DPCH.

Table 6.6B: DPCH Spreading Code, Timing offsets and level settings for TM5

Code (SF=128)

Timing offset (x256Tchip)

Level settings

( dB) (30 codes)

Level settings ( dB) (14 codes)

Level settings ( dB) (6 codes)

Level settings ( dB) (4 codes)*

15

86

-20

-17

-17

-15

23

134

-20

-19

-15

-15

68

52

-21

-19

-15

-18

76

45

-22

-20

-18

-12

82

143

-24

-18

-16

90

112

-21

-20

-17

5

59

-23

-25

11

23

-25

-23

17

1

-23

-20

27

88

-26

-22

64

30

-24

-21

72

18

-22

-22

86

30

-24

-19

94

61

-28

-20

3

128

-27

7

143

-26

13

83

-27

19

25

-25

21

103

-21

25

97

-21

31

56

-23

66

104

-26

70

51

-25

74

26

-24

78

137

-27

80

65

-26

84

37

-23

88

125

-25

89

149

-22

92

123

-24

Note *: Only applicable to Home BS

Table 6.6C: HS-SCCH Spreading Code, Timing offsets and level settings for TM5

Code (SF=128)

Timing offset (x256Tchip)

Level settings

( dB)

9

0

-15

29

0

-21

Table 6.6D: HS-PDSCH Spreading Code, Timing offsets, level settings for TM5

Code (SF=16)

Timing offset (x256Tchip)

Level settings

( dB) (8 codes)

Level settings ( dB) (4 codes)

Level settings ( dB) (2 codes)

4

0

-11

-8

-5

5

0

-11

-8

6

0

-11

7

0

-11

12

0

-11

-8

-5

13

0

-11

-8

14

0

-11

15

0

-11

6.1.1.4B Test Model 6 – TM6

This model shall be used for tests on:

– Relative CDE for base stations supporting HS-PDSCH transmission using 64QAM modulation

For Home base station, an additional option of this test model containing 4 HS-PDSCH + 4 DPCH is also specified. The conformance test shall be performed using the larger option that can be supported by the Home base station under test.

Each HS-PDSCH is modulated by 64QAM.

Table 6.6E: TM6 Active Channels

Type

Number of Channels

Fraction of

Power (%)

Level setting (dB)

Channelization Code

Timing offset (x256Tchip)

P-CCPCH+SCH

1

7.9

-11

1

0

Primary CPICH

1

7.9

-11

0

0

PICH

1

1.3

-19

16

120

S-CCPCH containing PCH (SF=256)

1

1.3

-19

3

0

DPCH

(SF=128)

30/4*

27.1 in total

see table 6.6F

see table 6.6F

see table 6.6F

HS-SCCH

2

4 in total

see table 6.6G

see table 6.6G

see table 6.6G

HS-PDSCH (64QAM)

8/4*

50.5 in total

see table 6.6H

see table 6.6H

see table 6.6H

Note *: 8 HS-PDSCH shall be taken together with 30 DPCH, and (for Home BS only) 4 HS-PDSCH shall be taken with 4 DPCH.

Table 6.6F: DPCH Spreading Code, Timing offsets and level settings for TM6

Code (SF=128)

Timing offset (x256Tchip)

Level settings

(dB) (30 codes)

Level settings

(dB) (4 codes)*

15

86

-17

-13

23

134

-17

-15

68

52

-18

-9

76

45

-19

-12

82

143

-21

90

112

-18

5

59

-20

11

23

-22

17

1

-20

27

88

-23

64

30

-21

72

18

-19

86

30

-21

94

61

-25

3

128

-24

7

143

-23

13

83

-24

19

25

-22

21

103

-18

25

97

-18

31

56

-20

66

104

-23

70

51

-22

74

26

-21

78

137

-24

80

65

-23

84

37

-22

88

125

-22

89

149

-22

92

123

-21

Note *: Only applicable to Home BS

Table 6.6G: HS-SCCH Spreading Code, Timing offsets and level settings for TM6

Code (SF=128)

Timing offset (x256Tchip)

Level settings

(dB)

9

0

-15

29

0

-21

Table 6.6H: HS-PDSCH Spreading Code, Timing offsets, level settings for TM6

Code (SF=16)

Timing offset (x256Tchip)

Level settings

(dB) (8 codes)

Level settings

(dB) (4 codes)*

4

0

-12

-9

5

0

-12

-9

6

0

-12

7

0

-12

12

0

-12

-9

13

0

-12

-9

14

0

-12

15

0

-12

Note *: Only applicable to Home BS

6.1.1.5 DPCH Structure of the Downlink Test Models

For the above test models the following structure is adopted for the DPCH. The DPDCH and DPCCH have the same power level. The timeslot structure should be as described by TS 25.211-slot format 10 and 6 that are reproduced in table 6.7.

Table 6.7: DPCH structure of the downlink Test Models

Slot Format

Channel Bit

Channel Symbol

SF

Bits/Frame

Bits/ Slot

DPDCH Bits/Slot

DPCCH Bits/Slot

#I

Rate (kbps)

Rate (ksps)

DPDCH

DPCCH

TOT

NData1

Ndata2

NTFCI

NTPC

Npilot

10

60

30

128

450

150

600

40

6

24

0

2

8

6

30

15

256

150

150

300

20

2

8

0

2

8

The test DPCH has frame structure so that the pilot bits are defined over 15 timeslots according to the relevant columns of TS 25.211, which are reproduced in table 6.8.

Table 6.8: Frame structure of DPCH

Npilot = 8

Symbol #

0

1

2

3

Slot #0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

00

01

00

10

11

11

10

01

11

01

10

10

00

00

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

10

10

01

00

01

10

00

00

10

11

01

11

00

11

11

The TPC bits alternate 00 / 11 starting with 00 in timeslot 0.

The aggregate 15 x 30 = 450 DPDCH bits per frame are filled with a PN9 sequence generated using the primitive trinomial . In case there are less data bits/frame needed then the first bits of the aggregate shall be selected. To ensure non-correlation of the PN9 sequences, each DPDCH shall use its channelization code as the seed for the PN sequence at the start of each frame, according to its timing offset.

The sequence shall be generated in a nine-stage shift register whose 5th and 9th stage outputs are added in a modulo‑two addition stage, and the result is fed back to the input of the first stage. The generator shall be seeded so that the sequence begins with the channelization code starting from the LSB, and followed by 2 consecutive ONEs for SF=128 and 1 consecutive ONE for SF=256.

Figure 6.2

6.1.1.6 Common channel Structure of the Downlink Test Models

6.1.1.6.1 P-CCPCH

The aggregate 15 x 18 = 270 P-CCPCH bits per frame are filled with a PN9 sequence generated using the primitive trinomial . Channelization code of the P-CCPCH is used as the seed for the PN sequence at the start of each frame.

The generator shall be seeded so that the sequence begins with the 8 bit channelization code starting from the LSB, and followed by a ONE.

6.1.1.6.2 PICH

PICH carries 18 Paging Indicators (Pq) sent in the following sequence from left to right [1 0 1 1 0 0 0 1 0 1 1 0 0 0 1 0 1 0]. This defines the 288 first bits of the PICH. No power is transmitted for the 12 remaining unused bits.

6.1.1.6.3 Primary scrambling code and SCH

The scrambling code should be 0.

Where multiple repetitions of the Test Model signals are being used to simulate a multi-carrier signal the scrambling code for the lower frequency is 0. Carriers added at successively higher frequencies use codes 1, 2,… and their frame structures are time offset by 1/5, 2/5… of a time slot duration.

The scrambling code defines the SSC sequence of the secondary SCH. In their active part, primary and secondary SCH share equally the power level defined for "PCCPCH+SCH".

6.1.1.6.4 S-CCPCH containing PCH

The aggregate 15 x 20 = 300 S-CCPCH bits per frame are used. Data bits are filled with a PN9 sequence generated using the primitive trinomial . In case there are less data bits/frame needed then the first bits of the aggregate shall be selected.. Channelization code of the S-CCPCH is used as the seed for the PN sequence at the start of each frame. For test purposes, any one of the four possible slot formats 0,1, 2 and 3 can be supported. The support for all four slot formats is not needed..

The generator shall be seeded so that the sequence begins with the 8 bit channelization code starting from the LSB, and followed by a ONE. The test on S-CCPCH has a frame structure so that the pilot bits are defined over 15 timeslots to the relevant columns of TS 25.211. The TFCI bits are filled with ONEs whenever needed.

6.1.1.7 HS-PDSCH Structure of the Downlink TM5

There are 640 bits per slot in a 16QAM-modulated HS-PDSCH. The aggregate 15 x 640 = 9600 bits per frame are filled with repetitions of a PN9 sequence generated using the primitive trinomial . To ensure non-correlation of the PN9 sequences, each HS-PDSCH shall use its channelization code multiplied by 23 as the seed for the PN sequence at the start of each frame.

The generator shall be seeded so that the sequence begins with the channelization code multiplied by 23 starting from the LSB.

Figure 6.2

6.1.1.8 HS-SCCH Structure of the Downlink Test Models 5 and 6

There are 40 bits per time slot in a HS-SCCH. The aggregate 15 x 40 = 600 bits per frame are filled with repetitions of a PN9 sequence generated using the primitive trinomial . Channelization code of the HS-SCCH is used as the seed for the PN sequence at the start of each frame. The generator shall be seeded so that the sequence begins with the channelization code starting from the LSB, and followed by 2 consecutive ONEs.

6.1.1.9 HS-PDSCH Structure of the Downlink TM6

There are 960 bits per slot in a 64QAM-modulated HS-PDSCH. The aggregate 15 x 960 = 14400 bits per frame are filled with repetitions of a PN9 sequence generated using the primitive trinomial . To ensure non-correlation of the PN9 sequences, each HS-PDSCH shall use its channelization code multiplied by 23 as the seed for the PN sequence at the start of each frame.

The generator shall be seeded so that the sequence begins with the channelization code multiplied by 23 starting from the LSB.

Figure 6.3