G.1 Statistical testing of Performance Requirements with throughput

38.521-43GPPNRPart 4: PerformanceRadio transmission and receptionRelease 17TSUser Equipment (UE) conformance specification

Tools: ARFCN - Frequency Conversion for 5G NR/LTE/UMTS/GSM

G.1.1 General

The test of receiver performance characteristics is twofold.

1. A signal or a combination of signals is offered to the RX port(s) of the receiver.

2. The ability of the receiver to demodulate /decode this signal is verified by measuring the throughput.

In (2) is the statistical aspect of the test and is treated here.

The minimum requirement for most receiver performance tests is either 70 % or 30 % of the maximum throughput.

All receiver performance tests are performed in fading conditions. In addition to the statistical considerations, this requires the definition of a minimum test time.

G.1.2 Mapping throughput to error ratio

a) The measured information bit throughput R is defined as the sum (in kilobits) of the information bit payloads successfully received during the test interval, divided by the duration of the test interval (in seconds).

b) In measurement practice the UE indicates successfully received information bit payload by signalling an ACK to the SS.
If payload is received, but damaged and cannot be decoded, the UE signals a NACK.

c) Only the ACK and NACK signals, not the data bits received, are accessible to the SS.
The number of bits is known in the SS from knowledge of what payload was sent.

d) For the reference measurement channel, applied for testing, the number of bits is different in different slots, however in a radio frame it is fixed during one test.

e) The time in the measurement interval is composed of successfully received slots (ACK), unsuccessfully received slots (NACK) and no reception at all (DTX-slots).

f) DTX-slots may occur regularly according the applicable reference measurement channel (regDTX).
In real live networks this is the time when other UEs are served. In TDD these are the UL and special slots.
regDTX vary from test to test but are fixed within the test.

g) Additional DTX-slots occur statistically when the UE is not responding ACK or NACK where it should. (statDTX)
This may happen when the UE was not expecting data or decided that the data were not intended for it.

The pass / fail decision is done by observing the:

– number of NACKs

– number of ACKs and

– number of statDTXs (regDTX is implicitly known to the SS)

The ratio (NACK + statDTX)/(NACK+ statDTX + ACK)is the Error Ratio (ER). Taking into account the time consumed by the ACK, NACK, and DTX-TTIs (regular and statistical), ER can be mapped unambiguously to throughput for any single reference measurement channel test.

G.1.3 Design of the test

The test is defined by the following design principles (see clause G.2, Theory):

1. The standard concept is applied. (not the early decision concept)

2. A second limit is introduced: The second limit is different, whether 30 % or 70 % throughput is tested.

3. To decide the test pass:

Supplier risk is applied based on the Bad DUT quality

To decide the test fail:

Customer Risk is applied based on the specified DUT quality

The test is defined by the following parameters:

1a) Limit Error Ratio = 0.3 (in case 70 % Throughput is tested) or

1b) Limit Throughput = 0.3 (in case 30 % Throughput is tested) or

1c) Limit Error Ratio = 0.01 (in case 1% BLER is tested)

2a) Bad DUT factor M=1.378 (selectivity)

2b) Bad DUT factor m=0.692 (selectivity)

2c) Bad DUT facor M=1.5 (selectivity)

justification see: TS 34.121 Clause F.6.3.3

3) Confidence level CL = 95 % (for specified DUT and Bad DUT-quality)

G.1.4 Pass Fail limit

Testing Throughput = 30 %, then the test limit is

Number of successes (ACK) / number of samples ≥ 59 / 233

Testing Throughput = 70 % then the test limit is

Number of fails (NACK and statDTX) / number of samples ≤ 66 / 184

Testing BLER = 1% then the test limit is

Number of fails (NACK and statDTX) / number of samples ≤ 163 / 13135

There are 3 distinct cases:

a) The duration for the number of samples (233, 184 or 13135) is greater than the minimum test time:

Then the number of samples (233, 184 or 13135) is predefined and the decision is done according to the number of events (59 successes, 66 fails or 163 fails)

b) Since subframe 0 and 5 contain less bits than the remaining subframes, it is allowed to predefine a number of samples contained in an integer number of frames. In this case test-limit-ratio applies.

c) The minimum test time is greater than the duration for the number of samples:

The minimum test time is predefined and the decision is done comparing the measured ratio at that instant against the test-limit-ratio.

NOTE: The test time for most of the tests is governed by the Minimum Test Time.

G.1.5 Minimum Test time

Editor’s Note: Simulation method to derive minimum test time for FR2 needs to be evaluated.

If a pass fail decision in clause G.1.4 can be achieved earlier than the minimum test time, then the test shall not be decided, but continued until the minimum test time is elapsed.

The tables below contain the minimum number of slots for FDD and TDD.

By simulations the minimum number of active subframes (carrying DL payload) was derived (MNAS), then adding inactive subframes to the active ones. (for TDD additional subframes contain no DL payload), then rounding up to full thousand.

Simulation method to derive minimum test time:

With a level, corresponding a throughput at the test limit (here 30 % or 70 % of the max. throughput) the preliminary throughput versus time converges towards the final throughput. The allowance of ± 0.2 dB around the above mentioned level is predefined by RAN5 to find the minimum test time. The allowance of ±0.2 dB maps through the function "final throughput versus level" into a throughput corridor. The minimum test time is achieved when the preliminary throughput escapes the corridor the last time. The two functions "final throughput versus level" and "preliminary throughput versus time" are simulation results, which are done individual for each demodulation scenario.

Figure G.1.5-1: Simulation method to derive minimum test time

Table G.1.5-1: Minimum Test time for PDSCH demodulation

TDD UL-DL pattern

Reference Channel

Propagation condition

Demodulation scenario (doppler speed)

Minimum number of active subframes (MNAS)

MNAS to MNS Scaling factor (Note 3)

Minimum Number of Subframes

(MNS) after rounding up to nearest thousand

MNS=

R.PDSCH.1-8.1 FDD

HST-750

750 Hz

6000 (Note 1)

1.0526

6400

R.PDSCH.1-8.2 FDD

HST-972

972 Hz

6000 (Note 1)

1.0526

6400

R.PDSCH.1-8.1 FDD

TDLC300-600

600 Hz

8000 (Note 1)

1.0526

9000

R.PDSCH.1-1.1 FDD

TDLB100-400

400 Hz

10000 (Note 1)

1.0526

11000

R.PDSCH.1-1.2 FDD, R.PDSCH.1-2.1 FDD, R.PDSCH.1-5.1 FDD

TDLC300-100

100 Hz

20000 (Note 1)

1.0526

22000

R.PDSCH.1-1.3 FDD, R.PDSCH.1-2.2 FDD, R.PDSCH.1-2.3 FDD, R.PDSCH.1-2.4 FDD, R.PDSCH.1-2.5 FDD, R.PDSCH.1-3.1 FDD, R.PDSCH.1-3.2 FDD, R.PDSCH.1-3.3 FDD, R.PDSCH.1-3.4 FDD, R.PDSCH.1-4.1 FDD, R.PDSCH.1-12.1 FDD, R.PDSCH.2-1.1 FDD

TDLA30-10

10 Hz

75000 (Note 1)

1.0526

79000

R.PDSCH.1-7.1 FDD, R.PDSCH.1-7.2 FDD

TDLA30-10

10 Hz

75000 (Note 1)

1.25

94000

R.PDSCH.1-8.3 FDD,

R.PDSCH.1-13.1 FDD,

R.PDSCH.1-13.2 FDD,

R.PDSCH.1-13.3 FDD,

R.PDSCH.1-13.4 FDD,

R.PDSCH.1-13.5 FDD,

R.PDSCH.1-14.1 FDD,

R.PDSCH.1-14.2 FDD,

R.PDSCH.1-14.3 FDD,

R.PDSCH.1-14.4 FDD

HST-SFN

870 Hz

30000 (Note 1)

1.0526

32000

R.PDSCH.1-8.4 FDD,

R.PDSCH.1-15.1 FDD,

R.PDSCH.1-15.2 FDD,

R.PDSCH.1-15.3 FDD,

R.PDSCH.1-15.4 FDD,

R.PDSCH.1-15.5 FDD,

R.PDSCH.1-16.1 FDD,

R.PDSCH.1-16.2 FDD,

R.PDSCH.1-16.3 FDD,

R.PDSCH.1-16.4 FDD

HST-DPS

870 Hz

30000 (Note 1)

1.0526

32000

FR1.15-1

R.PDSCH.1-1.1 TDD, R.PDSCH.1-1.2 TDD

TDLA30-10

10Hz

75000 (Note 1)

2.8571

215000

FR1.30-1A

R.PDSCH.2-1.1 TDD

TDLB100-400

400 Hz

10000 (Note 1)

1.2903

13000

FR1.30-1

R.PDSCH.2-1.2 TDD, R.PDSCH.2-2.1 TDD, R.PDSCH.2-7.1 TDD

TDLC300-100

100 Hz

20000 (Note 1)

1.2903

26000

FR1.30-1

R.PDSCH.2-2.2 TDD, R.PDSCH.2-2.3 TDD, R.PDSCH.2-2.4 TDD, R.PDSCH.2-2.5 TDD, R.PDSCH.2-3.1 TDD, R.PDSCH.2-3.2 TDD, R.PDSCH.2-3.3 TDD, R.PDSCH.2-3.4 TDD, R.PDSCH.2-4.1 TDD

TDLA30-10

10 Hz

75000 (Note 1)

1.2903

97000

FR1.30-1

R.PDSCH.2-1.3 TDD

TDLA30-10

10 Hz

75000 (Note 1)

1.4815

112000

FR1.30-2

R.PDSCH.2-5.1 TDD

TDLA30-10

10 Hz

75000 (Note 1)

1.2903

97000

FR1.30-2

R.PDSCH.2-17.1 TDD

TDLA30-10

10 Hz

75000 (Note 1)

375000

FR1.30-3

R.PDSCH.2-6.1 TDD

TDLA30-10

10 Hz

75000 (Note 1)

1.4815

112000

FR1.30-4

R.PDSCH.2-9.1 TDD

TDLA30-10

10 Hz

75000 (Note 1)

1.2903

97000

FR1.30-5

R.PDSCH.2-11.1 TDD

TDLB100-400

400Hz

10000 (Note 1)

1.2903

13000

FR1.30-6

R.PDSCH.2-12.1 TDD

TDLB100-400

400Hz

10000 (Note 1)

1.2903

13000

FR1.30-1

R.PDSCH.2-10.1 TDD

HST-1000

1000 Hz

15000 (Note 1)

1.4815

23000

FR1.30-1

R.PDSCH.2-10.1 TDD

HST-1667

1667 Hz

15000 (Note 1)

1.4815

23000

FR1.30-1

R.PDSCH.2-10.4 TDD,

R.PDSCH.2-19.1 TDD,

R.PDSCH.2-19.2 TDD,

R.PDSCH.2-19.3 TDD,

R.PDSCH.2-19.4 TDD,

R.PDSCH.2-19.5 TDD,

R.PDSCH.2-20.1 TDD,

R.PDSCH.2-20.2 TDD,

R.PDSCH.2-20.3 TDD,

R.PDSCH.2-20.4 TDD,

R.PDSCH.2-20.5 TDD,

R.PDSCH.2-21.1 TDD

HST-SFN

1667 Hz

30000 (Note 1)

1.4815

45000

FR1.30-1

R.PDSCH.2-10.5 TDD,

R.PDSCH.2-22.1 TDD,

R.PDSCH.2-22.2 TDD,

R.PDSCH.2-22.3 TDD,

R.PDSCH.2-22.4 TDD,

R.PDSCH.2-22.5 TDD,

R.PDSCH.2-23.1 TDD,

R.PDSCH.2-23.2 TDD,

R.PDSCH.2-23.3 TDD,

R.PDSCH.2-23.4 TDD,

R.PDSCH.2-23.5 TDD,

R.PDSCH.2-24.1 TDD

HST-DPS

1667 Hz

30000 (Note 1)

1.4815

45000

FR2.60-1

R.PDSCH.4-1.1 TDD

TDLA30-75

75 Hz

20000 (Note 2)

1.33

27000

FR2.120-1A

R.PDSCH.5-1.1 TDD

TDLC60-300

300 Hz

10000 (Note 2)

1.25

13000

FR2.120-1

R.PDSCH.5-2.1 TDD, R.PDSCH.5-2.2 TDD, R.PDSCH.5-2.3 TDD, R.PDSCH.5-3.1 TDD

TDLA30-300

300 Hz

10000 (Note 2)

1.25

13000

FR2.120-1

R.PDSCH.5-1.2 TDD

TDLA30-75

75 Hz

20000 (Note 2)

1.25

25000

FR2.120-2

R.PDSCH.5-4.1 TDD, R.PDSCH.5-5.1 TDD, R.PDSCH.5-5.2 TDD, R.PDSCH.5-6.1 TDD

TDLA30-75

75 Hz

20000 (Note 2)

1.33

27000

FR2.120-1

R.PDSCH.5-10.1 TDD

TDLD30-75

75 Hz

20000 (Note 2)

1.26

26000

Note 1: MNAS determined by simulations.

Note 2: For cases where MNS is not determined by simulations, use same MNAS as the similar case simulated (same doppler speed)

Note 3: MNS/MNAS ratio decided by scheduling pattern and is ratio of all slots to DL slots.

Table G.1.5-1a: Minimum Test time for PDSCH demodulation with 1% BLER

TDD UL-DL pattern	Reference Channel	Propagation condition	Demodulation scenario (doppler speed)	Minimum number of active subframes (MNAS)	MNAS to MNS Scaling factor (Note 3)	Minimum Number of Subframes (MNS) after rounding up to nearest thousand MNS=
NA	R.PDSCH.1-11.1 FDD R.PDSCH.1-11.2 FDD	TDLA30-10	10 Hz	[200000] (Note 1)	1.1111	[223000]
FR1.30-1	R.PDSCH.2-16.1 TDD R.PDSCH.2-16.2 TDD	TDLA30-10	10 Hz	[200000] (Note 1)	1.6667	[334000]
Note 1: MNAS determined by simulations. Note 2: For cases where MNS is not determined by simulations, use same MNAS as the similar case simulated (same doppler speed). Note 3: MNS/MNAS ratio decided by scheduling pattern (how much time is required to collect required number of active DL SFs).

Table G.1.5-2: Minimum Test time for PDCCH demodulation

Reference Channel	Demodulation scenario (doppler speed)	Minimum number of active subframes (MNAS)	MNAS to MNS Scaling factor (Note 3)	Minimum Number of Subframes (MNS) after rounding up to nearest thousand MNS=
R.PDCCH 1-1.1 FDD, R.PDCCH.1-1.3 FDD, R.PDCCH.1-2.1 FDD, R.PDCCH.1-2.2 FDD, R.PDCCH.1-2.3 FDD, R.PDCCH.1-2.4 FDD, R.PDCCH.1-2.5 FDD, R.PDCCH.1-2.6 FDD	10, 100, 400 Hz	100000 (Note 1)	1.0526	106000
R.PDCCH.2-1.1 TDD, R.PDCCH.2-1.2 TDD, R.PDCCH.2-2.1 TDD, R.PDCCH.2-1.3 TDD	10, 100, 400 Hz	100000 (Note 1)	1.2903	130000
R.PDCCH.5-1.1 TDD, R.PDCCH.5-1.2 TDD, R.PDCCH.5-1.3 TDD, R.PDCCH.5-2.1 TDD	75, 300 Hz	100000 (Note 2)	1.25	130000
Note 1: MNAS determined by simulations. Note 2: For cases where MNS is not determined by simulations, use same MNAS as the similar case simulated (same doppler speed) Note 3: MNS/MNAS ratio decided by scheduling pattern and is ratio of all slots to DL slots.