4.5 Coding for HS-DSCH
25.2223GPPMultiplexing and channel coding (TDD)Release 17TS
Figure 15 illustrates the overall concept of transport-channel coding for HS-DSCH. Data arrives at the coding unit in the form of one transport block once every TTI. The TTI is 5 ms for 1.28 Mcps TDD and 10 ms for 3.84 Mcps TDD / 7.68Mcps TDD.
For 1.28 Mcps TDD, in the case of multiple-frequency transmission in one TTI, a number of transport blocks arrive at the coding unit, in which the number of transport blocks equals the number of frequencies used. Each transport block for each frequency shall be coded separately as the following coding step.
For 1.28Mcps TDD, in the case of MIMO dual stream transmission in one TTI, two transport blocks arrive at the coding unit. Each transport block for each data stream shall be coded separately as the following coding step.
The following coding steps for HS-DSCH can be identified:
– add CRC to each transport block (see subclause 4.5.1);
– code block segmentation (see subclause 4.5.2);
– channel coding (see subclause 4.5.3);
– hybrid ARQ (see subclause 4.5.4);
– bit scrambling (see subclause 4.5.5);
– interleaving for HS-DSCH (see subclause 4.5.6);
– constellation re-arrangement for 16QAM and 64QAM (see subclause 4.5.7);
– mapping to physical channels (see subclause 4.5.8).
The coding steps for HS-DSCH are shown in figure 15.
Figure 15: Coding chain for HS-DSCH
In the following the number of transport blocks is always one. When referencing non HS-DSCH formulae which are used in correspondence with HS-DSCH formulae the convention is used that transport block subscripts may be omitted (e.g. Xi when i is always 1 may be written X).
4.5.1 CRC attachment for HS-DSCH
A CRC of size 24 bits is calculated and added per HS-DSCH TTI. The CRC polynomial is defined in 4.2.1.1 with the following specific parameters: i = 1, L1 = 24 bits.
4.5.2 Code block segmentation for HS-DSCH
Code block segmentation for the HS-DSCH transport channel shall be done with the general method described in 4.2.2.2 above with the following specific parameters.
There will only be one transport block, i = 1. The bits bim1, bim2, bim3,…bimB input to the block are mapped to the bits xi1, xi2, xi3,…xiX1 directly. It follows that X1 = B. Note that the bits x referenced here refer only to the internals of the code block segmentation function. The output bits from the code block segmentation function are oir1, oir2, oir3,…oirK.
The value of Z = 5114 for turbo coding shall be used.
4.5.3 Channel coding for HS-DSCH
Channel coding for the HS-DSCH transport channel shall be done with the general method described in 4.2.3 above with the following specific parameters.
There will be a maximum of one transport block, i = 1. The rate 1/3 turbo coding shall be used.
4.5.4 Hybrid ARQ for HS-DSCH
The hybrid ARQ functionality matches the number of bits at the output of the channel coder to the total number of bits of the HS-PDSCH set to which the HS-DSCH is mapped. The hybrid ARQ functionality is controlled by the redundancy version (RV) parameters. The exact set of bits at the output of the hybrid ARQ functionality depends on the number of input bits, the number of output bits, and the RV parameters.
The hybrid ARQ functionality consists of two rate-matching stages and a virtual buffer as shown in the figure below.
The first rate matching stage matches the number of input bits to the virtual IR buffer, information about which is provided by higher layers. Note that, if the number of input bits does not exceed the virtual IR buffering capability, the first rate-matching stage is transparent.
The second rate matching stage matches the number of bits after first rate matching stage to the number of physical channel bits available in the HS-PDSCH set in the TTI.
Figure 16: HS-DSCH hybrid ARQ functionality
4.5.4.1 HARQ bit separation
The HARQ bit separation function shall be performed in the same way as bit separation for turbo encoded TrCHs in 4.2.7.2 above.
4.5.4.2 HARQ First Rate Matching Stage
HARQ first stage rate matching for the HS-DSCH transport channel shall be done with the general method described in 4.2.7.1.2 above with the following specific parameters.
The maximum number of soft channel bits available in the virtual IR buffer is NIR which is signalled from higher layers for each HARQ process. The number of coded bits in a TTI before rate matching is NTTI this is deduced from information signalled from higher layers and parameters signalled on the HS-SCCH for each TTI. Note that HARQ processing and physical layer storage occurs independently for each HARQ process currently active.
If NIR is greater than or equal to NTTI (i.e. all coded bits of the corresponding TTI can be stored) the first rate matching stage shall be transparent. This can, for example, be achieved by setting eminus = 0. Note that no repetition is performed.
If NIR is smaller than NTTI the parity bit streams are punctured as in 4.2.7.1.2 above by setting the rate matching parameter where the subscripts i and l refer to transport channel and transport format in the referenced sub-clause. Note the negative value is expected when the rate matching implements puncturing. Bits selected for puncturing which appear as in the algorithm in 4.2.7 above shall be discarded and not counted in the totals for the streams through the virtual IR buffer.
4.5.4.3 HARQ Second Rate Matching Stage
HARQ second stage rate matching for the HS-DSCH transport channel shall be done with the general method described in 4.2.7.3 above with the following specific parameters. Bits selected for puncturing which appear as in the algorithm in 4.2.7.3 above shall be discarded and are not counted in the streams towards the bit collection.
The parameters of the second rate matching stage depend on the value of the RV parameters s and r. The parameter s can take the value 0 or 1 to distinguish between transmissions that prioritise systematic bits (s = 1) and non systematic bits (s = 0). The parameter r (range 0 to rmax-1) changes the initial error variable eini in the case of puncturing. In case of repetition both parameters r and s change the initial error variable eini. The parameters Xi, eplus and eminus are calculated as per table 14below.
Denote the number of bits before second rate matching as Nsys for the systematic bits, Np1 for the parity 1 bits, and Np2 for the parity 2 bits, respectively. For the HS-DSCH, denote the number of timeslots used as T, the number of codes per timeslot as C and the number of bits available in timeslot t as Ut, where Ut = and is the number of bits available in physical channel of timeslot t as defined in [7]. Ndata is the number of bits available to the HS-DSCH in one TTI and is defined as . The rate matching parameters are determined as follows.
For , puncturing is performed in the second rate matching stage. The number of transmitted systematic bits in a transmission is for a transmission that prioritises systematic bits and for a transmission that prioritises non systematic bits.
For repetition is performed in the second rate matching stage. A similar repetition rate in all bit streams is achieved by setting the number of transmitted systematic bits to .
The number of parity bits in a transmission is: and for the parity 1 and parity 2 bits, respectively.
Table 14 below summarizes the resulting parameter choice for the second rate matching stage.
Table 14: Parameters for HARQ second rate matching
|
Xi |
eplus |
eminus |
|
|
Systematic |
|||
|
Parity 1 |
|||
|
Parity 2 |
The rate matching parameter eini is calculated for each bit stream according to the RV parameters r and s using
in the case of puncturing, i.e.,, and
for repetition, i.e.,.
Where 
and 
is the total number of redundancy versions allowed by varying 
as defined in 4.6.1.4.
Note that rmax varies depending on the modulation mode, i.e. for 16QAM and 64QAM rmax = 2 and for QPSK rmax = 4.
Note: For the modulo operation the following clarification is used: the value of (x mod y) is strictly in the range of 0 to y-1 (i.e. -1 mod 10 = 9).
4.5.4.4 HARQ bit collection
The HARQ bit collection is achieved using a rectangular interleaver of size 
.
The number of rows and columns are determined from:
for 64QAM
for 16QAM
for QPSK
where Ndata is used as defined in 4.5.4.3 above.
Data is written into the interleaver column by column, and read out of the interleaver column by column, starting from the first column.
Nt,sys is the number of transmitted systematic bits. Intermediate values Nr and Nc are calculated using:
and .
If Nc = 0 and Nr > 0, the systematic bits are written into rows 1…Nr.
Otherwise systematic bits are written into rows 1…Nr+1 in the first Nc columns and, if Nr > 0, also into rows 1…Nr in the remaining Ncol-Nc columns.
The remaining space is filled with parity bits. The parity bits are written column wise into the remaining rows of the respective columns. Parity 1 and 2 bits are written in alternating order, starting with a parity 2 bit in the first available column with the lowest index number.
In the case of 64QAM for each column the bits are read out of the interleaver in the order row1, row2, row3, row4, row 5, row6. In the case of 16QAM for each column the bits are read out of the interleaver in the order row 1, row 2, row 3, row 4. In the case of QPSK for each column the bits are read out of the interleaver in the order row1, row2.
4.5.5 Bit scrambling
The bit scrambling for HS-DSCH shall be done with the general method described in subclause 4.2.9.
4.5.6 Interleaving for HS-DSCH
The interleaving for TDD is done over all bits in the TTI, as shown in figure 17 when QPSK modulation is being used for the HS-DSCH, and figure 18 when 16-QAM modulation is being used, and figure 18a when 64QAM modulation is being used. The bits input to the block interleaver are denoted by s1, s2, s3, …, sR , where R is the number of bits in one TTI.
Figure 17: Interleaver structure for HS-DSCH with QPSK modulation
For QPSK, the interleaver is a block interleaver and consists of bits input to a matrix with padding, the inter-column permutation for the matrix and bits output from the matrix with pruning. The output bit sequence from the block interleaver is derived as follows:
(1) The number of columns of the matrix is 30. The columns of the matrix are numbered 0, 1, 2, …, 29 from left to right.
(2) Determine the number of rows of the matrix, R2, by finding minimum integer R2 such that R 30 R2. The rows of rectangular matrix are numbered 0, 1, 2, …, R2 – 1 from top to bottom.
(3) Write the input bit sequence s1, s2, s3, …, sR into the R2 30 matrix row by row starting with bit y1 in column 0 of row 0:
where yk = sk for k = 1, 2, …, R and, if R < 30R2, dummy bits are inserted for k = R+1, R+2, …, 30R2. These dummy bits are pruned away from the output of the matrix after the inter-column permutation.
(4) Perform the inter-column permutation for the matrix based on the pattern that is shown in Table 7, where P2(j) is the original column position of the j-th permuted column. After permutation of the columns, the bits are denoted by y’k.
(5) The output of the block interleaver is the bit sequence read out column by column from the inter-column permuted R230 matrix. The output is pruned by deleting dummy bits that were padded to the input of the matrix before the inter-column permutation, i.e. bits y’k that corresponds to bits yk with k > R are removed from the output. The bits after interleaving are denoted by v1, v2, v3, …, vR, where v1 corresponds to the bit y’k with smallest index k after pruning, v2 to the bit y’k with second smallest index k after pruning, and so on.
Figure 18: Interleaver structure for HS-DSCH with 16-QAM modulation
For 16QAM, a second identical interleaver operates in parallel to the first. For both interleavers, R2 is chosen to be the minimum integer that satisfies R ≤ 60 R2. The output bits from the bit scrambling operation are divided pairwise between the interleavers: bits sk and sk+1 go to the first interleaver and bits sk+2 and sk+3 go to the second interleaver, where k mod 4 = 1. Bits are collected pairwise from the interleavers: bits vk and vk+1 are obtained from the first interleaver and bits vk+2 and vk+3 are obtained from the second interleaver, where again k mod 4 = 1.
Figure 18a: Interleaver structure for HS-DSCH with 64-QAM modulation
The interleaving for TDD is done over all bits in the TTI, as shown in figure 18a when 64QAM modulation is being used for the HS-DSCH. The bits input to the block interleaver are denoted by s1, s2, s3, …, sR , where R is the number of bits in one TTI.
For 64QAM, two identical interleavers operate in parallel to the first. For all interleavers, R2 is chosen to be the minimum integer that satisfies R ≤ 90 R2. The output bits from the bit scrambling operation are divided into three parts of different interleavers: bits sk and sk+1 go to the first interleaver, bits sk+2 and sk+3 go to the second interleaver and bits sk+4 and sk+5 go to the third interleaver, where k mod 6 = 1. Bits are collected accordingly from the interleavers: bits vk and vk+1 are obtained from the first interleaver, bits vk+2 and vk+3 are obtained from the second interleaver and bits vk+4 and vk+5 are obtained from the third interleaver, where again k mod 6 = 1.
4.5.7 Constellation re-arrangement for 16 QAM and 64 QAM
This function only applies to 16 QAM modulated bits. In case of QPSK it is transparent.
The following table 15 describes the operations that produce the different rearrangements.
The bits of the input sequence are mapped in groups of 4 so that vk, vk+1, vk+2, vk+3 are used, where k mod 4 = 1.
Table 15: Constellation re-arrangement for 16 QAM
|
Constellation version parameter b |
Output bit sequence |
Operation |
|
0 |
None |
|
|
1 |
Swapping MSBs with LSBs |
|
|
2 |
Inversion of the logical values of LSBs |
|
|
3 |
Swapping MSBs with LSBs, and inversion of the logical values of LSBs |
The output bit sequences from the table above map to the output bits in groups of 4, i.e. rk, rk+1, rk+2, rk+3, where k mod 4 = 1.
The following table 15a describes the operations that produce the different rearrangements of 64 QAM.
The bits of the input sequence are mapped in groups of 6 so that vk, vk+1, vk+2, vk+3, vk+4, vk+5 are used, where k mod 6 = 1.
Table 15a: Constellation re-arrangement for 64 QAM
|
Constellation version parameter b |
Output bit sequence |
Operation |
|
0 |
None |
|
|
1 |
Swapping MSBs and LSBs. Inversion of Middle SBs |
|
|
2 |
Left circular shift of pair of SBs. Inversion of Middle SBs |
|
|
3 |
Inversion of Middle SBs |
The output bit sequences from the table above map to the output bits in groups of 6, i.e. rk, rk+1, rk+2, rk+3, rk+4, rk+5, where k mod 6 = 1.
4.5.8 Physical channel mapping for HS-DSCH
The HS-PDSCH is defined in [7]. The bits input to the physical channel mapping are denoted by r1, r2, …, rR, where R is the number of physical channel bits in the allocation for the current TTI. These bits are mapped to the physical channel bits, {wt,p,j : t = 1, 2, …, T; p = 1, 2, …, C; j = 1, 2, …, Ut,p}, where t is the timeslot index, T is the number of timeslots in the allocation message, p is the physical channel index, C is the number of codes per timeslot in the allocation message, j is the physical channel bit index and Ut,p is the number of bits for the physical channel p in timeslot t. The timeslot index, t, increases with increasing timeslot number; the physical channel index, p, increases with increasing channelisation code index, and the physical channel bit index, j, increases with increasing physical channel bit position in time. If TS0 is included in the allocation message, TS0 has the maximum timeslot index while the timeslot index of any other timeslot increases with increasing timeslot number.
The bits rk shall be mapped to the PhCHs according to the following rule :
Define {yt,k : k = 1, 2, …, } to be the set of bits to be transmitted in timeslot t as follows :
for k = 1, 2, …,
for k = 1, 2, …,
…
for k = 1, 2, …,
When the modulation level applied to the physical channels is 16- QAM :
The physical channel p used to transmit the kth bit in the sequence yt,k is :
if (k <= Ut,1·C)
If p is odd then :
where
If p is even then :
where
else
If p is odd then :
where
If p is even then :
where
Otherwise, when the modulation level applied to the physical channels is QPSK :
The physical channel p used to transmit the kth bit in the sequence yt,k is :
if (k <= Ut,1·C)
If p is odd then :
where
If p is even then :
where
else
If p is odd then :
where
If p is even then :
where
When the modulation level applied to the physical channels is 64-QAM:
The physical channel p used to transmit the kth bit in the sequence yt,k is:
If p is odd then :
where
If p is even then :
where