B.1 Downlink power control timing

25.2143GPPPhysical layer procedures (FDD)Release 17TS

The power control timing described in this annex should be seen as an example on how the control bits have to be placed in order to permit a short TPC delay.

In order to maximise the cell radius distance within which one-slot control delay is achieved, the frame timing of an uplink DPCH is delayed by 1024 chips from that of the corresponding downlink DPCH measured at the UE antenna.

Responding to a downlink TPC command, the UE shall change its uplink DPCH output power at the beginning of the first uplink pilot field after the TPC command reception. Responding to an uplink TPC command, the UTRAN access point shall change its DPCH output power at the beginning of the next downlink pilot field after the reception of the whole TPC command. Note that in soft handover, the TPC command is sent over one slot when DPC_MODE is 0 and over three slots when DPC_MODE is 1. Note also that the delay from the uplink TPC command reception to the power change timing is not specified for UTRAN. The UE shall decide and send TPC commands on the uplink based on the downlink SIR measurement. For the DPCH, the TPC command field on the uplink starts, when measured at the UE antenna, 512 chips after the end of the downlink pilot field. The UTRAN access point shall decide and send TPC commands based on the uplink SIR measurement. However, the SIR measurement periods are not specified either for UE nor UTRAN.

Figure B.1 illustrates an example of transmitter power control timings when a DPCH is configured on the downlink, with a slot format that contains pilot bits.

Figure B.1: Transmitter power control timing for DPCH when downlink DPCH slot format contains pilot bits

Figure B.1A illustrates an example of transmitter power control timings when a DPCH is configured on the downlink, with a slot format that does not contain pilot bits.

Figure B.1A: Transmitter power control timing for DPCH when downlink DPCH slot format does not contain pilot bits

Figure B.2 illustrates an example of transmitter power control timings when the F-DPCH is configured on the downlink and the F-DPCH TPC offset N_OFF1 of all the radio links in the RLS is 0 or 2(see Table 16C of [1]). Figure B.2a illustrates an example of transmitter power control timings for the radio link whose F-DPCH TPC offset N_OFF1 = 0 or 2, when the F-DPCH is configured on the downlink, and the F-DPCH TPC offset N_OFF1 of at least one other radio link in the RLS is > 2. Figure B.3 illustrates an example of transmitter power control timings when the F-DPCH is configured on the downlink and the F-DPCH TPC offset N_OFF1 of the radio link is larger than 2. Figure B.4 illustrates an example of transmitter power control timings when the F-DPCH is configured on the downlink and the F-DPCH TPC offset N_OFF1 of the radio link is larger than 14 when uplink DPCCH slot format #4 is used.

Figure B.2: Transmitter power control timing for F-DPCH with TPC offsets N_OFF1 of 0 or 2 when F-DPCH TPC offset N_OFF1 of all the radio links in the RLS is 0 or 2

Figure B.2a: Transmitter power control timing for F-DPCH with TPC offsets N_OFF1 of 0 or 2 when the F-DPCH TPC offset N_OFF1 of at least one other radio link in the RLS is > 2

Figure B.3: Transmitter power control timing for F-DPCH with a TPC offset N_OFF1 larger than 2

Figure B.4: Transmitter power control timing for F-DPCH with a TPC offset N_OFF1 larger than 14 with uplink DPCCH slot format #4