A.1 Antenna verification

25.2143GPPPhysical layer procedures (FDD)Release 17TS

In closed loop mode 1, if channel estimates are taken from the Primary CPICH, the performance will also suffer if the UE cannot detect errors since the channel estimates will be taken for the incorrect phase settings. To mitigate this problem, antenna verification can be done, which can make use of antenna specific pilot patterns of the dedicated physical channel. The antenna verification can be implemented with several different algorithms. A straightforward algorithm can use a 4-hypothesis test per slot. Alternatively, a simplified beam former verification (SBV) requiring only a 2-hypothesis test per slot can be used.

Consider

Then define the variable x₀ as 0 if the above inequality holds good and x₀ =  otherwise.

Similarly consider

then define the variable x₁ as -/2 if the above inequality holds good and x₁ = /2 oherwise.

Whether x₀ or x₁ is to be calculated for each slot is given by the following table , where the first row contains the UL slot index of the feedback bit to be verified.

UL	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14
	x0	x1	x0	x1	x0	x1	x0	x1	x0	x1	x0	x1	x0	x1	x0

The estimate for the transmitted phase is now obtained from

where:

– the x_i ­values are used corresponding to the current slot and the previous slot taking into account the end-of-frame adjustment and the used CL timing adjustment delay

– is the i‘th estimated channel tap of antenna 2 using the CPICH;

– is the i‘th estimated channel tap of antenna 2 using the DPCCH;

 ² is the DPCH Pilot SNIR/ CPICH SNIR;

– is the noise plus interference power on the i‘th path.

In normal operation the a priori probability for selected pilot pattern is assumed to be 96% (assuming there are 4% of errors in the feedback channel for power control and antenna selection).