5 Downlink spreading and modulation
25.2133GPPRelease 17Spreading and modulation (FDD)TS
5.1 Spreading
Figure 8 illustrates the spreading operation for all physical channel except SCH. The spreading operation includes a modulation mapper stage successively followed by a channelisation stage, an IQ combining stage and a scrambling stage. All the downlink physical channels are then combined as specified in sub subclause 5.1.5.
The non-spread downlink physical channels, except SCH, AICH, E-HICH and E-RGCH consist of a sequence of 3-valued digits taking the values 0, 1 and "DTX". Note that "DTX" is only applicable to those downlink physical channels that support DTX transmission.
Figure 8: Spreading for all downlink physical channels except SCH
NOTE: Although subclause 5.1 has been reorganized in this release, the spreading operation as specified for the DL channels in the previous release remains unchanged.
5.1.1 Modulation mapper
Table 3A defines which of the IQ mapping specified in subclauses 5.1.1.1 and 5.1.1.2 may be used for the physical channel being processed.
Table 3A: IQ mapping
|
Physical channel |
IQ mapping |
|
HS-PDSCH |
QPSK, 16QAM or 64QAM |
|
S-CCPCH used for MBSFN |
QPSK or 16QAM |
|
All other channels (except the SCH) |
QPSK |
5.1.1.1 QPSK
For all channels, except AICH, E-HICH and E‑RGCH, the input digits shall be mapped to real-valued symbols as follows: the binary value "0" is mapped to the real value +1, the binary value "1" is mapped to the real value –1 and "DTX" is mapped to the real value 0.
For the indicator channels using signatures (AICH), the real-valued input symbols depend on the exact combination of the indicators to be transmitted as specified in [2] subclauses 5.3.3.7, 5.3.3.8 and 5.3.3.9.For the E-HICH and the E‑RGCH the input is a real valued symbol sequence as specified in [2]
Each pair of two consecutive real-valued symbols is first converted from serial to parallel and mapped to an I and Q branch. The definition of the modulation mapper is such that even and odd numbered symbols are mapped to the I and Q branch respectively. For all QPSK channels except the indicator channels using signatures, symbol number zero is defined as the first symbol in each frame or sub-frame. For the indicator channels using signatures, symbol number zero is defined as the first symbol in each access slot.
5.1.1.2 16QAM
In case of 16QAM, a set of four consecutive binary symbols nk, nk+1, nk+2, nk+3 (with k mod 4 = 0) is serial-to-parallel converted to two consecutive binary symbols (i1= nk, i2= nk+2) on the I branch and two consecutive binary symbols (q1= nk+1, q2= nk+3) on the Q branch and then mapped to 16QAM by the modulation mapper as defined in table 3B.
The I and Q branches are then both spread to the chip rate by the same real-valued channelisation code Cch,16,m. The channelisation code sequence shall be aligned in time with the symbol boundary. The sequences of real-valued chips on the I and Q branch are then treated as a single complex-valued sequence of chips. This sequence of chips from all multi-codes is summed and then scrambled (complex chip-wise multiplication) by a complex-valued scrambling code Sdl,n. The scrambling code is applied aligned with the scrambling code applied to the P-CCPCH.
Table 3B: 16QAM modulation mapping
|
i1q1i2q2 |
I branch |
Q branch |
|
0000 |
0.4472 |
0.4472 |
|
0001 |
0.4472 |
1.3416 |
|
0010 |
1.3416 |
0.4472 |
|
0011 |
1.3416 |
1.3416 |
|
0100 |
0.4472 |
-0.4472 |
|
0101 |
0.4472 |
-1.3416 |
|
0110 |
1.3416 |
-0.4472 |
|
0111 |
1.3416 |
-1.3416 |
|
1000 |
-0.4472 |
0.4472 |
|
1001 |
-0.4472 |
1.3416 |
|
1010 |
-1.3416 |
0.4472 |
|
1011 |
-1.3416 |
1.3416 |
|
1100 |
-0.4472 |
-0.4472 |
|
1101 |
-0.4472 |
-1.3416 |
|
1110 |
-1.3416 |
-0.4472 |
|
1111 |
-1.3416 |
-1.3416 |
In the case of 16-QAM on S-CCPCH, a sequence of four consecutive symbols nk, nk+1, nk+2, nk+3 (with k mod 4 = 0) at the input to the modulation mapper may contain values from the set 0, 1, and "DTX". In the event that all 4 bits of the quadruple are DTX bits, the output from the modulation mapping on both the I and Q branches is equal to the real value 0.
For all other cases, all DTX bits in the quadruple are replaced with other non-DTX bits from the quadruple according to the following:
The quadruple consists of two bit pairs, {nk,nk+2} on the I branch, and {nk+1,nk+3} on the Q branch. For any bit pair, if a non-DTX bit is available in the same pair, the DTX bit shall be replaced with the non-DTX bit value. If a non-DTX bit is not available in the same pair, the two DTX bits in that pair shall be replaced by the non-DTX bits in the other pair (using the same bit ordering when the other pair contains two non-DTX bits).
The bit positions and values of non-DTX bits in the quadruple are not affected.
5.1.1.3 64QAM
In case of 64QAM, a set of six consecutive binary symbols nk, nk+1, nk+2, nk+3, nk+4, nk+5 (with k mod 6 = 0) is serial-to-parallel converted to three consecutive binary symbols (i1= nk, i2= nk+2, i3= nk+4) on the I branch and three consecutive binary symbols (q1= nk+1, q2= nk+3, q3= nk+5) on the Q branch and then mapped to 64QAM by the modulation mapper as defined in table 3C.
The I and Q branches are then both spread to the chip rate by the same real-valued channelisation code Cch,16,m. The channelisation code sequence shall be aligned in time with the symbol boundary. The sequences of real-valued chips on the I and Q branch are then treated as a single complex-valued sequence of chips. This sequence of chips from all multi-codes is summed and then scrambled (complex chip-wise multiplication) by a complex-valued scrambling code Sdl,n. The scrambling code is applied aligned with the scrambling code applied to the P-CCPCH.
Table 3C: 64QAM modulation mapping
|
i1q1i2q2 i3q3 |
I branch |
Q branch |
i1q1i2q2 i3q3 |
I branch |
Q branch |
|
|
000000 |
0.6547 |
0.6547 |
100000 |
-0.6547 |
0.6547 |
|
|
000001 |
0.6547 |
0.2182 |
100001 |
-0.6547 |
0.2182 |
|
|
000010 |
0.2182 |
0.6547 |
100010 |
-0.2182 |
0.6547 |
|
|
000011 |
0.2182 |
0.2182 |
100011 |
-0.2182 |
0.2182 |
|
|
000100 |
0.6547 |
1.0911 |
100100 |
-0.6547 |
1.0911 |
|
|
000101 |
0.6547 |
1.5275 |
100101 |
-0.6547 |
1.5275 |
|
|
000110 |
0.2182 |
1.0911 |
100110 |
-0.2182 |
1.0911 |
|
|
000111 |
0.2182 |
1.5275 |
100111 |
-0.2182 |
1.5275 |
|
|
001000 |
1.0911 |
0.6547 |
101000 |
-1.0911 |
0.6547 |
|
|
001001 |
1.0911 |
0.2182 |
101001 |
-1.0911 |
0.2182 |
|
|
001010 |
1.5275 |
0.6547 |
101010 |
-1.5275 |
0.6547 |
|
|
001011 |
1.5275 |
0.2182 |
101011 |
-1.5275 |
0.2182 |
|
|
001100 |
1.0911 |
1.0911 |
101100 |
-1.0911 |
1.0911 |
|
|
001101 |
1.0911 |
1.5275 |
101101 |
-1.0911 |
1.5275 |
|
|
001110 |
1.5275 |
1.0911 |
101110 |
-1.5275 |
1.0911 |
|
|
001111 |
1.5275 |
1.5275 |
101111 |
-1.5275 |
1.5275 |
|
|
010000 |
0.6547 |
-0.6547 |
110000 |
-0.6547 |
-0.6547 |
|
|
010001 |
0.6547 |
-0.2182 |
110001 |
-0.6547 |
-0.2182 |
|
|
010010 |
0.2182 |
-0.6547 |
110010 |
-0.2182 |
-0.6547 |
|
|
010011 |
0.2182 |
-0.2182 |
110011 |
-0.2182 |
-0.2182 |
|
|
010100 |
0.6547 |
-1.0911 |
110100 |
-0.6547 |
-1.0911 |
|
|
010101 |
0.6547 |
-1.5275 |
110101 |
-0.6547 |
-1.5275 |
|
|
010110 |
0.2182 |
-1.0911 |
110110 |
-0.2182 |
-1.0911 |
|
|
010111 |
0.2182 |
-1.5275 |
110111 |
-0.2182 |
-1.5275 |
|
|
011000 |
1.0911 |
-0.6547 |
111000 |
-1.0911 |
-0.6547 |
|
|
011001 |
1.0911 |
-0.2182 |
111001 |
-1.0911 |
-0.2182 |
|
|
011010 |
1.5275 |
-0.6547 |
111010 |
-1.5275 |
-0.6547 |
|
|
011011 |
1.5275 |
-0.2182 |
111011 |
-1.5275 |
-0.2182 |
|
|
011100 |
1.0911 |
-1.0911 |
111100 |
-1.0911 |
-1.0911 |
|
|
011101 |
1.0911 |
-1.5275 |
111101 |
-1.0911 |
-1.5275 |
|
|
011110 |
1.5275 |
-1.0911 |
111110 |
-1.5275 |
-1.0911 |
|
|
011111 |
1.5275 |
-1.5275 |
111111 |
-1.5275 |
-1.5275 |
5.1.2 Channelisation
For all physical channels (except SCH) the I and Q branches shall be spread to the chip rate by the same real-valued channelisation code Cch,SF,m, i.e. the output for each input symbol on the I and the Q branches shall be a sequence of SF chips corresponding to the channelisation code chip sequence multiplied by the real-valued symbol. The channelisation code sequence shall be aligned in time with the symbol boundary.
5.1.3 IQ combining
The real valued chip sequence on the Q branch shall be complex multiplied with j and summed with the corresponding real valued chip sequence on the I branch, thus resulting in a single complex valued chip sequence.
5.1.4 Scrambling
The sequence of complex valued chips shall be scrambled (complex chip-wise multiplication) by a complex-valued scrambling code Sdl,n. In case of P-CCPCH, the scrambling code shall be applied aligned with the P-CCPCH frame boundary, i.e. the first complex chip of the spread P-CCPCH frame is multiplied with chip number zero of the scrambling code. In case of other downlink channels, the scrambling code shall be applied aligned with the scrambling code applied to the P‑CCPCH. In this case, the scrambling code is thus not necessarily applied aligned with the frame boundary of the physical channel to be scrambled.
5.1.5 Channel combining
Figure 9 illustrates how different downlink channels are combined. Each complex-valued spread channel, corresponding to point S in Figure 8, may be separately weighted by a weight factor Gi. The complex-valued P-SCH and S-SCH, as described in [2], subclause 5.3.3.5, may be separately weighted by weight factors Gp and Gs. All downlink physical channels shall then be combined using complex addition.
Figure 9: Combining of downlink physical channels
5.2 Code generation and allocation
5.2.1 Channelisation codes
The channelisation codes of figure 8 are the same codes as used in the uplink, namely Orthogonal Variable Spreading Factor (OVSF) codes that preserve the orthogonality between downlink channels of different rates and spreading factors. The OVSF codes are defined in figure 4 in subclause 4.3.1.
The channelisation code for the Primary CPICH is fixed to Cch,256,0 and the channelisation code for the Primary CCPCH is fixed to Cch,256,1.The channelisation codes for all other physical channels are assigned by UTRAN.
With the spreading factor 512 a specific restriction is applied. When the code word Cch,512,n, with n=0,2,4….510, is used in soft handover, then the code word Cch,512,n+1 is not allocated in the cells where timing adjustment is to be used. Respectively if Cch,512,n, with n=1,3,5….511 is used, then the code word Cch,512,n-1 is not allocated in the cells where timing adjustment is to be used. This restriction shall not apply in cases where timing adjustments in soft handover are not used with spreading factor 512.
When compressed mode is implemented by reducing the spreading factor by 2, the OVSF code used for compressed frames is:
– Cch,SF/2,n/2 if ordinary scrambling code is used.
– Cch,SF/2,n mod SF/2 if alternative scrambling code is used (see subclause 5.2.2);
where Cch,SF,n is the channelisation code used for non-compressed frames.
For F-DPCH, the spreading factor is always 256.
For HS-PDSCH, the spreading factor is always 16.
For HS-SCCH, the spreading factor is always 128.
Channelisation-code-set information over HS-SCCH is mapped in following manner: the OVSF codes shall be allocated in such a way that they are positioned in sequence in the code tree. That is, for P multicodes at offset O the following codes are allocated:
Cch,16,O … Cch,16, O+P-1
The number of multicodes and the corresponding offset for HS-PDSCHs mapped from a given HS-DSCH is signalled by HS-SCCH.
For E-HICH and for E-RGCH, the spreading factor shall always be 128. In each cell, the E‑RGCH and E-HICH assigned to a UE shall be configured with the same channelisation code.
For E-AGCH, the spreading factor shall always be 256.
For F-TPICH, the spreading factor shall always be 256.
For E-ROCH, the spreading factor shall always be 256.
5.2.2 Scrambling code
A total of 218-1 = 262,143 scrambling codes, numbered 0…262,142 can be generated. However not all the scrambling codes are used. The scrambling codes are divided into 512 sets each of a primary scrambling code and 15 secondary scrambling codes.
The primary scrambling codes consist of scrambling codes n=16*i where i=0…511. The i:th set of secondary scrambling codes consists of scrambling codes 16*i+k, where k=1…15.
There is a one-to-one mapping between each primary scrambling code and 15 secondary scrambling codes in a set such that i:th primary scrambling code corresponds to i:th set of secondary scrambling codes.
Hence, according to the above, scrambling codes k = 0, 1, …, 8191 are used. Each of these codes are associated with a left alternative scrambling code and a right alternative scrambling code, that may be used for compressed frames. The left alternative scrambling code corresponding to scrambling code k is scrambling code number k + 8192, while the right alternative scrambling code corresponding to scrambling code k is scrambling code number k + 16384. The alternative scrambling codes can be used for compressed frames. In this case, the left alternative scrambling code is used if n<SF/2 and the right alternative scrambling code is used if nSF/2, where cch,SF,n is the channelisation code used for non-compressed frames. The usage of alternative scrambling code for compressed frames is signalled by higher layers for each physical channel respectively.
In case F-DPCH is configured in the downlink, the same scrambling code and OVSF code shall be used in F-DPCH compressed frames and normal frames.
In the case that F-TPICH is configured in the downlink, the same scrambling code and OVSF code shall be used in F-TPICH compressed frames and normal frames.
The set of primary scrambling codes is further divided into 64 scrambling code groups, each consisting of 8 primary scrambling codes. The j:th scrambling code group consists of primary scrambling codes 16*8*j+16*k, where j=0..63 and k=0..7.
Each cell is allocated one and only one primary scrambling code. The primary CCPCH, primary CPICH, PICH, MICH, AICH and S-CCPCH carrying PCH or BCH shall always be transmitted using the primary scrambling code. The other downlink physical channels may be transmitted with either the primary scrambling code or a secondary scrambling code from the set associated with the primary scrambling code of the cell.
In MBSFN operations, the S-CCPCH carries FACH only and shall always be transmitted using the primary scrambling code. The same primary CCPCH, primary CPICH, MICH and S-CCPCH may be transmitted from multiple cells using the same primary scrambling code when part of MBSFN operations.
The mixture of primary scrambling code and no more than one secondary scrambling code for one CCTrCH is allowable. In compressed mode during compressed frames, these can be changed to the associated left or right scrambling codes as described above, i.e. in these frames, the total number of different scrambling codes may exceed two.
In the case of CCTrCH of type of HS-DSCH then all the HS-PDSCH channelisation codes and HS-SCCH that a single UE may receive from a single cell shall be under a single scrambling code (either the primary or a secondary scrambling code).
In each cell, the F-DPCH, E‑RGCH, E-HICH, E-AGCH, E-ROCH and F-TPICH assigned to a UE shall be configured with same scrambling code as the assigned phase reference (primary or secondary CPICH).
In each cell the UE may be configured simultaneously with at most two scrambling codes.
The scrambling code sequences are constructed by combining two real sequences into a complex sequence. Each of the two real sequences are constructed as the position wise modulo 2 sum of 38400 chip segments of two binary m-sequences generated by means of two generator polynomials of degree 18. The resulting sequences thus constitute segments of a set of Gold sequences. The scrambling codes are repeated for every 10 ms radio frame. Let x and y be the two sequences respectively. The x sequence is constructed using the primitive (over GF(2)) polynomial 1+X7+X18 . The y sequence is constructed using the polynomial 1+X5+X7+ X10+X18 .
The sequence depending on the chosen scrambling code number n is denoted zn, in the sequel. Furthermore, let x(i), y(i) and zn(i) denote the i:th symbol of the sequence x, y, and zn, respectively.
The m-sequences xand y are constructed as:
Initial conditions:
– x is constructed with x (0)=1, x(1)= x(2)=…= x (16)= x (17)=0.
– y(0)=y(1)= … =y(16)= y(17)=1.
Recursive definition of subsequent symbols:
– x(i+18) =x(i+7) + x(i) modulo 2, i=0,…,218-20.
– y(i+18) = y(i+10)+y(i+7)+y(i+5)+y(i) modulo 2, i=0,…, 218-20.
The n:th Gold code sequence zn, n=0,1,2,…,218-2, is then defined as:
– zn(i) = x((i+n) modulo (218 – 1)) + y(i) modulo 2, i=0,…, 218-2.
These binary sequences are converted to real valued sequences Zn by the following transformation:
Finally, the n:th complex scrambling code sequence Sdl,n is defined as:
– Sdl,n(i) = Zn(i) + j Zn((i+131072) modulo (218-1)), i=0,1,…,38399.
Note that the pattern from phase 0 up to the phase of 38399 is repeated.
Figure 10: Configuration of downlink scrambling code generator
5.2.3 Synchronisation codes
5.2.3.1 Code generation
The primary synchronisation code (PSC), Cpsc is constructed as a so-called generalised hierarchical Golay sequence. The PSC is furthermore chosen to have good aperiodic auto correlation properties.
Define:
– a = <x1, x2, x3, …, x16> = <1, 1, 1, 1, 1, 1, -1, -1, 1, -1, 1, -1, 1, -1, -1, 1>
The PSC is generated by repeating the sequence a modulated by a Golay complementary sequence, and creating a complex-valued sequence with identical real and imaginary components. The PSC Cpsc is defined as:
– Cpsc = (1 + j) <a, a, a, -a, -a, a, -a, -a, a, a, a, -a, a, -a, a, a>;
where the leftmost chip in the sequence corresponds to the chip transmitted first in time.
The 16 secondary synchronization codes (SSCs), {Cssc,1,…,C ssc,16}, are complex-valued with identical real and imaginary components, and are constructed from position wise multiplicationof a Hadamard sequence and a sequence z, defined as:
– z = <b, b, b, -b, b, b, -b, -b, b, -b, b, -b, -b, -b, -b, -b>, where
– b = <x1, x2, x3, x4, x5, x6, x7, x8, -x9, –x10, -x11, –x12, -x13, –x14, –x15, –x16> and x1, x2 , …, x15, x16, are same as in the definition of the sequence a above.
The Hadamard sequences are obtained as the rows in a matrix H8 constructed recursively by:
The rows are numbered from the top starting with row 0 (the all ones sequence).
Denote the n:th Hadamard sequence as a row of H8 numbered from the top, n = 0, 1, 2, …, 255, in the sequel.
Furthermore, let hn(i) and z(i) denote the i:th symbol of the sequence hn and z, respectively where i = 0, 1, 2, …, 255 and i = 0 corresponds to the leftmost symbol.
The k:th SSC, Cssc,k, k = 1, 2, 3, …, 16 is then defined as:
– Cssc,k = (1 + j) <hm(0) z(0), hm(1) z(1), hm(2) z(2), …, hm(255) z(255)>;
where m = 16(k – 1) and the leftmost chip in the sequence corresponds to the chip transmitted first in time.
5.2.3.2 Code allocation of SSC
The 64 secondary SCH sequences are constructed such that their cyclic-shifts are unique, i.e., a non-zero cyclic shift less than 15 of any of the 64 sequences is not equivalent to some cyclic shift of any other of the 64 sequences. Also, a non-zero cyclic shift less than 15 of any of the sequences is not equivalent to itself with any other cyclic shift less than 15. Table 4 describes the sequences of SSCs used to encode the 64 different scrambling code groups. The entries in table 4 denote what SSC to use in the different slots for the different scrambling code groups, e.g. the entry "7" means that SSC Cssc,7 shall be used for the corresponding scrambling code group and slot.
Table 4: Allocation of SSCs for secondary SCH
|
Scrambling Code Group |
slot number |
||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
#0 |
#1 |
#2 |
#3 |
#4 |
#5 |
#6 |
#7 |
#8 |
#9 |
#10 |
#11 |
#12 |
#13 |
#14 |
|
|
Group 0 |
1 |
1 |
2 |
8 |
9 |
10 |
15 |
8 |
10 |
16 |
2 |
7 |
15 |
7 |
16 |
|
Group 1 |
1 |
1 |
5 |
16 |
7 |
3 |
14 |
16 |
3 |
10 |
5 |
12 |
14 |
12 |
10 |
|
Group 2 |
1 |
2 |
1 |
15 |
5 |
5 |
12 |
16 |
6 |
11 |
2 |
16 |
11 |
15 |
12 |
|
Group 3 |
1 |
2 |
3 |
1 |
8 |
6 |
5 |
2 |
5 |
8 |
4 |
4 |
6 |
3 |
7 |
|
Group 4 |
1 |
2 |
16 |
6 |
6 |
11 |
15 |
5 |
12 |
1 |
15 |
12 |
16 |
11 |
2 |
|
Group 5 |
1 |
3 |
4 |
7 |
4 |
1 |
5 |
5 |
3 |
6 |
2 |
8 |
7 |
6 |
8 |
|
Group 6 |
1 |
4 |
11 |
3 |
4 |
10 |
9 |
2 |
11 |
2 |
10 |
12 |
12 |
9 |
3 |
|
Group 7 |
1 |
5 |
6 |
6 |
14 |
9 |
10 |
2 |
13 |
9 |
2 |
5 |
14 |
1 |
13 |
|
Group 8 |
1 |
6 |
10 |
10 |
4 |
11 |
7 |
13 |
16 |
11 |
13 |
6 |
4 |
1 |
16 |
|
Group 9 |
1 |
6 |
13 |
2 |
14 |
2 |
6 |
5 |
5 |
13 |
10 |
9 |
1 |
14 |
10 |
|
Group 10 |
1 |
7 |
8 |
5 |
7 |
2 |
4 |
3 |
8 |
3 |
2 |
6 |
6 |
4 |
5 |
|
Group 11 |
1 |
7 |
10 |
9 |
16 |
7 |
9 |
15 |
1 |
8 |
16 |
8 |
15 |
2 |
2 |
|
Group 12 |
1 |
8 |
12 |
9 |
9 |
4 |
13 |
16 |
5 |
1 |
13 |
5 |
12 |
4 |
8 |
|
Group 13 |
1 |
8 |
14 |
10 |
14 |
1 |
15 |
15 |
8 |
5 |
11 |
4 |
10 |
5 |
4 |
|
Group 14 |
1 |
9 |
2 |
15 |
15 |
16 |
10 |
7 |
8 |
1 |
10 |
8 |
2 |
16 |
9 |
|
Group 15 |
1 |
9 |
15 |
6 |
16 |
2 |
13 |
14 |
10 |
11 |
7 |
4 |
5 |
12 |
3 |
|
Group 16 |
1 |
10 |
9 |
11 |
15 |
7 |
6 |
4 |
16 |
5 |
2 |
12 |
13 |
3 |
14 |
|
Group 17 |
1 |
11 |
14 |
4 |
13 |
2 |
9 |
10 |
12 |
16 |
8 |
5 |
3 |
15 |
6 |
|
Group 18 |
1 |
12 |
12 |
13 |
14 |
7 |
2 |
8 |
14 |
2 |
1 |
13 |
11 |
8 |
11 |
|
Group 19 |
1 |
12 |
15 |
5 |
4 |
14 |
3 |
16 |
7 |
8 |
6 |
2 |
10 |
11 |
13 |
|
Group 20 |
1 |
15 |
4 |
3 |
7 |
6 |
10 |
13 |
12 |
5 |
14 |
16 |
8 |
2 |
11 |
|
Group 21 |
1 |
16 |
3 |
12 |
11 |
9 |
13 |
5 |
8 |
2 |
14 |
7 |
4 |
10 |
15 |
|
Group 22 |
2 |
2 |
5 |
10 |
16 |
11 |
3 |
10 |
11 |
8 |
5 |
13 |
3 |
13 |
8 |
|
Group 23 |
2 |
2 |
12 |
3 |
15 |
5 |
8 |
3 |
5 |
14 |
12 |
9 |
8 |
9 |
14 |
|
Group 24 |
2 |
3 |
6 |
16 |
12 |
16 |
3 |
13 |
13 |
6 |
7 |
9 |
2 |
12 |
7 |
|
Group 25 |
2 |
3 |
8 |
2 |
9 |
15 |
14 |
3 |
14 |
9 |
5 |
5 |
15 |
8 |
12 |
|
Group 26 |
2 |
4 |
7 |
9 |
5 |
4 |
9 |
11 |
2 |
14 |
5 |
14 |
11 |
16 |
16 |
|
Group 27 |
2 |
4 |
13 |
12 |
12 |
7 |
15 |
10 |
5 |
2 |
15 |
5 |
13 |
7 |
4 |
|
Group 28 |
2 |
5 |
9 |
9 |
3 |
12 |
8 |
14 |
15 |
12 |
14 |
5 |
3 |
2 |
15 |
|
Group 29 |
2 |
5 |
11 |
7 |
2 |
11 |
9 |
4 |
16 |
7 |
16 |
9 |
14 |
14 |
4 |
|
Group 30 |
2 |
6 |
2 |
13 |
3 |
3 |
12 |
9 |
7 |
16 |
6 |
9 |
16 |
13 |
12 |
|
Group 31 |
2 |
6 |
9 |
7 |
7 |
16 |
13 |
3 |
12 |
2 |
13 |
12 |
9 |
16 |
6 |
|
Group 32 |
2 |
7 |
12 |
15 |
2 |
12 |
4 |
10 |
13 |
15 |
13 |
4 |
5 |
5 |
10 |
|
Group 33 |
2 |
7 |
14 |
16 |
5 |
9 |
2 |
9 |
16 |
11 |
11 |
5 |
7 |
4 |
14 |
|
Group 34 |
2 |
8 |
5 |
12 |
5 |
2 |
14 |
14 |
8 |
15 |
3 |
9 |
12 |
15 |
9 |
|
Group 35 |
2 |
9 |
13 |
4 |
2 |
13 |
8 |
11 |
6 |
4 |
6 |
8 |
15 |
15 |
11 |
|
Group 36 |
2 |
10 |
3 |
2 |
13 |
16 |
8 |
10 |
8 |
13 |
11 |
11 |
16 |
3 |
5 |
|
Group 37 |
2 |
11 |
15 |
3 |
11 |
6 |
14 |
10 |
15 |
10 |
6 |
7 |
7 |
14 |
3 |
|
Group 38 |
2 |
16 |
4 |
5 |
16 |
14 |
7 |
11 |
4 |
11 |
14 |
9 |
9 |
7 |
5 |
|
Group 39 |
3 |
3 |
4 |
6 |
11 |
12 |
13 |
6 |
12 |
14 |
4 |
5 |
13 |
5 |
14 |
|
Group 40 |
3 |
3 |
6 |
5 |
16 |
9 |
15 |
5 |
9 |
10 |
6 |
4 |
15 |
4 |
10 |
|
Group 41 |
3 |
4 |
5 |
14 |
4 |
6 |
12 |
13 |
5 |
13 |
6 |
11 |
11 |
12 |
14 |
|
Group 42 |
3 |
4 |
9 |
16 |
10 |
4 |
16 |
15 |
3 |
5 |
10 |
5 |
15 |
6 |
6 |
|
Group 43 |
3 |
4 |
16 |
10 |
5 |
10 |
4 |
9 |
9 |
16 |
15 |
6 |
3 |
5 |
15 |
|
Group 44 |
3 |
5 |
12 |
11 |
14 |
5 |
11 |
13 |
3 |
6 |
14 |
6 |
13 |
4 |
4 |
|
Group 45 |
3 |
6 |
4 |
10 |
6 |
5 |
9 |
15 |
4 |
15 |
5 |
16 |
16 |
9 |
10 |
|
Group 46 |
3 |
7 |
8 |
8 |
16 |
11 |
12 |
4 |
15 |
11 |
4 |
7 |
16 |
3 |
15 |
|
Group 47 |
3 |
7 |
16 |
11 |
4 |
15 |
3 |
15 |
11 |
12 |
12 |
4 |
7 |
8 |
16 |
|
Group 48 |
3 |
8 |
7 |
15 |
4 |
8 |
15 |
12 |
3 |
16 |
4 |
16 |
12 |
11 |
11 |
|
Group 49 |
3 |
8 |
15 |
4 |
16 |
4 |
8 |
7 |
7 |
15 |
12 |
11 |
3 |
16 |
12 |
|
Group 50 |
3 |
10 |
10 |
15 |
16 |
5 |
4 |
6 |
16 |
4 |
3 |
15 |
9 |
6 |
9 |
|
Group 51 |
3 |
13 |
11 |
5 |
4 |
12 |
4 |
11 |
6 |
6 |
5 |
3 |
14 |
13 |
12 |
|
Group 52 |
3 |
14 |
7 |
9 |
14 |
10 |
13 |
8 |
7 |
8 |
10 |
4 |
4 |
13 |
9 |
|
Group 53 |
5 |
5 |
8 |
14 |
16 |
13 |
6 |
14 |
13 |
7 |
8 |
15 |
6 |
15 |
7 |
|
Group 54 |
5 |
6 |
11 |
7 |
10 |
8 |
5 |
8 |
7 |
12 |
12 |
10 |
6 |
9 |
11 |
|
Group 55 |
5 |
6 |
13 |
8 |
13 |
5 |
7 |
7 |
6 |
16 |
14 |
15 |
8 |
16 |
15 |
|
Group 56 |
5 |
7 |
9 |
10 |
7 |
11 |
6 |
12 |
9 |
12 |
11 |
8 |
8 |
6 |
10 |
|
Group 57 |
5 |
9 |
6 |
8 |
10 |
9 |
8 |
12 |
5 |
11 |
10 |
11 |
12 |
7 |
7 |
|
Group 58 |
5 |
10 |
10 |
12 |
8 |
11 |
9 |
7 |
8 |
9 |
5 |
12 |
6 |
7 |
6 |
|
Group 59 |
5 |
10 |
12 |
6 |
5 |
12 |
8 |
9 |
7 |
6 |
7 |
8 |
11 |
11 |
9 |
|
Group 60 |
5 |
13 |
15 |
15 |
14 |
8 |
6 |
7 |
16 |
8 |
7 |
13 |
14 |
5 |
16 |
|
Group 61 |
9 |
10 |
13 |
10 |
11 |
15 |
15 |
9 |
16 |
12 |
14 |
13 |
16 |
14 |
11 |
|
Group 62 |
9 |
11 |
12 |
15 |
12 |
9 |
13 |
13 |
11 |
14 |
10 |
16 |
15 |
14 |
16 |
|
Group 63 |
9 |
12 |
10 |
15 |
13 |
14 |
9 |
14 |
15 |
11 |
11 |
13 |
12 |
16 |
10 |
5.3 Modulation
5.3.1 Modulating chip rate
The modulating chip rate is 3.84 Mcps.
5.3.2 Modulation
Modulation of the complex-valued chip sequence generated by the spreading process is shown in Figure 11 below.
Figure 11: Downlink modulation
The pulse-shaping characteristics are described in [4].
Annex A (informative):
Generalised Hierarchical Golay Sequences