4.3 Code generation and allocation
25.2133GPPRelease 17Spreading and modulation (FDD)TS
4.3.1 Channelisation codes
4.3.1.1 Code definition
The channelisation codes of figure 1 are Orthogonal Variable Spreading Factor (OVSF) codes that preserve the orthogonality between a user’s different physical channels. The OVSF codes can be defined using the code tree of figure 4.
Figure 4: Codetree for generation of Orthogonal Variable Spreading Factor (OVSF) codes
In figure 4, the channelisation codes are uniquely described as C_{ch,SF,k}, where SF is the spreading factor of the code and k is the code number, 0 k SF1.
Each level in the code tree defines channelisation codes of length SF, corresponding to a spreading factor of SF in figure 4.
The generation method for the channelisation code is defined as:
,
The leftmost value in each channelisation code word corresponds to the chip transmitted first in time.
4.3.1.2 Code allocation for dedicated physical channels
NOTE: Although subclause 4.3.1.2 has been reorganized in this release, the spreading operation for DPCCH and DPDCH remains unchanged as compared to the previous release.
4.3.1.2.1 Code allocation for DPCCH/ SDPCCH/DPDCH/DPCCH2
For the DPCCH, SDPCCH and DPDCHs the following applies:
– The DPCCH shall always be spread by code c_{c} = C_{ch,256,0.}
– The SDPCCH shall always be spread by code c_{sc} = C_{ch,256,31.}
_{– }The DPCCH2 shall be spread with code c_{c2} as specified in table 1C.5.
– When only one DPDCH is to be transmitted, DPDCH_{1} shall be spread by code c_{d,1} = C_{ch,SF,k} where SF is the spreading factor of DPDCH_{1} and k= SF / 4.
– When more than one DPDCH is to be transmitted, all DPDCHs have spreading factors equal to 4. DPDCH_{n} shall be spread by the the code c_{d,n }= C_{ch,4,k }, where k = 1 if n {1, 2}, k = 3 if n {3, 4}, and k = 2 if n {5, 6}.
Table 1C.5: Channelisation code of DPCCH2
Nmaxdpdch (as defined in subclause 4.2.1) 
Channelisation code c_{c2} 
0 
C_{ch,256,34} 
≥1 
C_{ch,256,3} 
If a power control preamble is used to initialise a DCH, the channelisation code for the DPCCH during the power control preamble shall be the same as that to be used afterwards.
4.3.1.2.2 Code allocation for HSDPCCH when the UE is not configured in MIMO mode with four transmit antennas in any cell
The HSDPCCH shall be spread with code c_{hs} as specified in table 1D. If Secondary_Cell_Enabled is greater than 3 HSDPCCH_{2} shall be spread with code c_{hs} as specified in table 1D.1.
If Secondary_Cell_Enabled as defined in [6] is 0 or 1 or if Secondary_Cell_Enabled is 2 and MIMO is not configured in any cell, HSDPCCH slot format #0 as defined in [2] is used.
If Secondary_Cell_Enabled is 2 and MIMO is configured in at least one cell or if Secondary_Cell_Enabled is 3, HSDPCCH slot format #1 as defined in [2] is used.
If Secondary_Cell_Enabled is greater than 3, HSDPCCH slot format #1 as defined in [2] is used.
Table 1D: channelisation code of HSDPCCH
N_{maxdpdch} (as defined in subclause 4.2.1) 
Channelisation code c_{hs} 

Secondary_Cell_Enabled is 0, 1, 2 or 3 
Secondary_Cell_Enabled is greater than 3 

HSDPCCH slot format #0 [2] 
HSDPCCH slot format #1 [2] 
HSDPCCH slot format #1 [2] 

0 
C_{ ch,256,33} 
C_{ ch,128,16} 
C_{ ch,128,16} 
1 
C_{ch,256,64} 
C_{ ch,128,32} 
C_{ ch,128,16} 
2,4,6 
C_{ch,256,1} 
N/A 
N/A 
3,5 
C_{ch,256,32} 
N/A 
N/A 
Table 1D.1: channelisation code of HSDPCCH_{2} if Secondary_Cell_Enabled is greater than 3.
N_{maxdpdch} (as defined in subclause 4.2.1) 
Channelisation code c_{hs} 
Secondary_Cell_Enabled is greater than 3 

HSDPCCH slot format #1 [2] 

0 
C_{ ch,128,16} 
1 
C_{ ch,128,16} 
4.3.1.2.2A Code allocation for HSDPCCH when the UE is configured in MIMO mode with four transmit antennas in at least one cell
If Secondary_Cell_Enabled as defined in [6] is 0 or 1, HSDPCCH slot format #1 as defined in [2] is used. HSDPCCH shall be spread with code c_{hs} as specified in table 1D.2.
If Secondary_Cell_Enabled is 2:
– If the UE is configured in MIMO mode with four transmit antennas in all cells, HSDPCCH slot format #1 as defined in [2] is used for both HSDPCCH and HSDPCCH_{2}. HSDPCCH shall be spread with code c_{hs} as specified in table 1D.2 and HSDPCCH_{2 }spread with code c_{hs} as specified in table 1D.3.
– If the number of cells configured in MIMO mode with four transmit antennas is less than 3 and if the UE is configured in MIMO mode with four transmit antennas either in the primary or in the 1^{st} secondary serving cell or both, then HSDPCCH slot format #1 as defined in [2] is used for HSDPCCH. HSDPCCH shall be spread with code c_{hs} as specified in table 1D.2.
– If the number of cells configured in MIMO mode with four transmit antennas is less than 3 and if the UE is not configured in MIMO mode with four transmit antennas in the primary and the 1^{st} secondary serving cell then HSDPCCH slot format #0 as defined in [2] is used for HSDPCCH. HSDPCCH shall be spread with code c_{hs} as specified in table 1D.4.
– If the number of cells configured in MIMO mode with four transmit antennas is less than 3 and if the UE is configured in MIMO mode with four transmit antennas in the 2^{nd} secondary serving cell then HSDPCCH slot format #1 as defined in [2] is used for HSDPCCH_{2}. HSDPCCH_{2 }spread with code c_{hs} as specified in table 1D.3.
– If the number of cells configured in MIMO mode with four transmit antennas is less than 3 and if the UE is not configured in MIMO mode with four transmit antennas in the 2^{nd }secondary serving cell then HSDPCCH slot format #0 as defined in [2] is used for HSDPCCH_{2}. HSDPCCH_{2 }spread with code c_{hs} as specified in table 1D.5.
If Secondary_Cell_Enabled is 3:
– If the UE is configured in MIMO mode with four transmit antennas in more than 2 cells HSDPCCH slot format #1 as defined in [2] is used for both HSDPCCH and HSDPCCH_{2}. HSDPCCH shall be spread with code c_{hs} as specified in table 1D.2 and HSDPCCH_{2 }spread with code c_{hs} as specified in table 1D.3.
– If the number of cells configured in MIMO mode with four transmit antennas is less than 3 and if the UE is configured in MIMO mode with four transmit antennas either in the primary or in the 1^{st} secondary serving cell or both, then HSDPCCH slot format #1 as defined in [2] is used for HSDPCCH. HSDPCCH shall be spread with code c_{hs} as specified in table 1D.2.
– If the number of cells configured in MIMO mode with four transmit antennas is less than 3 and if the UE is not configured in MIMO mode with four transmit antennas in the primary and the 1^{st} secondary serving cell then HSDPCCH slot format #0 as defined in [2] is used for HSDPCCH. HSDPCCH shall be spread with code c_{hs} as specified in table 1D.4.
– If the number of cells configured in MIMO mode with four transmit antennas is less than 3 and if the UE is configured in MIMO mode with four transmit antennas in the 2^{nd }serving or in the 3^{rd} serving secondary cell or both then HSDPCCH slot format #1 as defined in [2] is used for HSDPCCH_{2}. HSDPCCH_{2 }spread with code c_{hs} as specified in table 1D.3.
– If the number of cells configured in MIMO mode with four transmit antennas is less than 3 and if the UE is not configured in MIMO mode with four transmit antennas in the 2^{nd} and the 3^{rd} secondary serving cell then HSDPCCH slot format #0 as defined in [2] is used for HSDPCCH_{2}. HSDPCCH_{2 }spread with code c_{hs} as specified in table 1D.5.
Table 1D.2: channelisation code of HSDPCCH if Secondary_Cell_Enabled is 0 or 1 or 2 or 3 and the UE is configured in MIMO mode with four transmit antennas in any cell
N_{maxdpdch} (as defined in subclause 4.2.1) 
Channelisation code c_{hs}, Secondary_Cell_Enabled is 0, 1 
Channelisation code c_{hs}, Secondary_Cell_Enabled is 2, 3 
HSDPCCH slot format #1 [2] 
HSDPCCH slot format #1 [2] 

0 
C_{ch,128,16} 
C_{ch,128,16} 
1 
C_{ch,128,32} 
C_{ch,128,16} 
Table 1D.3: channelisation code of HSDPCCH_{2} if Secondary_Cell_Enabled is 2 or 3 and the UE is configured in MIMO mode with four transmit antennas in any cell
N_{maxdpdch} (as defined in subclause 4.2.1) 
Channelisation code c_{hs} 
Channelisation code c_{hs} 
HSDPCCH slot format #0 [2] 
HSDPCCH slot format #1 [2] 

0 
C_{ch,256,32} 
C_{ch,128,16} 
1 
C_{ch,256,32} 
C_{ch,128,16} 
Table 1D.4: channelisation code of HSDPCCH if Secondary_Cell_Enabled is greater than 1 and the UE is not configured in MIMO mode with four transmit antennas in the primary and the 1^{st} secondary serving cell.
N_{maxdpdch} (as defined in subclause 4.2.1) 
Channelisation code c_{hs} 
Secondary_Cell_Enabled is greater than 1 

HSDPCCH slot format #0 [2] 

0 
C_{ ch,256,33} 
1 
C_{ ch,256,64} 
Table 1D.5: channelisation code of HSDPCCH_{2} if Secondary_Cell_Enabled is equal to 3 and the UE is not configured in MIMO mode with four transmit antennas in the 2^{nd} and the 3^{rd} secondary serving cell or if Secondary_Cell_Enabled is equal to 2 and the UE is not configured in MIMO mode with four transmit antennas in the 2^{nd} secondary serving cell.
N_{maxdpdch} (as defined in subclause 4.2.1) 
Channelisation code c_{hs} 
Secondary_Cell_Enabled is greater than 1 

HSDPCCH slot format #0 [2] 

0 
C_{ ch,256,33} 
1 
C_{ ch,256,64} 
4.3.1.2.3 Code allocation for EDPCCH/EDPDCH
The EDPCCH shall be spread with channelisation code c_{ec} = C_{ch,256,1}.
EDPDCH_{k} shall be spread with channelisation code c_{ed,k}. The sequence c_{ed,k} depends on N_{maxdpdch} and the spreading factor selected for the corresponding frame or subframe as specified in [7]; it shall be selected according to table 1E.
Table 1E: Channelisation code for EDPDCH
N_{maxdpdch} 
EDPDCH_{k} 
Channelisation code_{ }C_{ed,k} 
0 
EDPDCH_{1} 
C_{ch,SF,SF/4} if SF 4 C_{ch,2,1} if SF = 2 
EDPDCH_{2} 
C_{ch,4,1} if SF = 4 C_{ch,2,1} if SF = 2 

EDPDCH_{3} EDPDCH_{4} 
C_{ch,4,1} 

1 
EDPDCH_{1} 
C_{ch,SF,SF/2} 
EDPDCH_{2} 
C_{ch,4,2} if SF = 4 C_{ch,2,1} if SF = 2 
NOTE: When more than one EDPDCH is transmitted, the respective channelisation codes used for EDPDCH_{1} and EDPDCH_{2} are always the same.
4.3.1.2.4 Code allocation for SEDPCCH/SEDPDCH
The SEDPCCH shall be spread with channelisation code c_{sec} = C_{ch,256,1}.
SEDPDCH_{k} shall be spread with channelisation code c_{sed,k}. The sequence c_{sed,k} shall be selected according to table 1F.
Table 1F: Channelisation code for SEDPDCH
N_{maxdpdch} 
SEDPDCH_{k} 
Channelisation code_{ }C_{sed,k} 
0 
SEDPDCH_{1} SEDPDCH_{2} 
C_{ch,2,1} 
SEDPDCH_{3} SEDPDCH_{4} 
C_{ch,4,1} 
NOTE: Either none or all four SEDPDCHs are transmitted.
4.3.1.3 Code allocation for PRACH message part
The preamble signature s, 0 s 15, points to one of the 16 nodes in the codetree that corresponds to channelisation codes of length 16. The subtree below the specified node is used for spreading of the message part. The control part is spread with the channelisation code c_{c} (as shown in subclause 4.2.2.2) of spreading factor 256 in the lowest branch of the subtree, i.e. c_{c} = C_{ch,256,m} where m = 16s + 15. The data part uses any of the channelisation codes from spreading factor 32 to 256 in the uppermost branch of the subtree. To be exact, the data part is spread by channelisation code c_{d} = C_{ch,SF,m} and SF is the spreading factor used for the data part and m = SFs/16.
4.3.1.4 Void
4.3.1.5 Void
4.3.2 Scrambling codes
4.3.2.1 General
All uplink physical channels on an activated uplink frequency shall be scrambled with a complexvalued scrambling code. The dedicated physical channels may be scrambled by either a long or a short scrambling code, defined in subclause 4.3.2.4. The PRACH message part shall be scrambled with a long scrambling code, defined in subclause 4.3.2.5. There are 2^{24} long and 2^{24} short uplink scrambling codes. Uplink scrambling codes are assigned by higher layers.
The long scrambling code is built from constituent long sequences defined in subclause 4.3.2.2, while the constituent short sequences used to build the short scrambling code are defined in subclause 4.3.2.3.
4.3.2.2 Long scrambling sequence
The long scrambling sequences c_{long,1,n} and c_{long,2,n} are constructed from position wise modulo 2 sum of 38400 chip segments of two binary msequences generated by means of two generator polynomials of degree 25. Let x, and y be the two msequences respectively. The x sequence is constructed using the primitive (over GF(2)) polynomial X^{25}+X^{3}+1. The y sequence is constructed using the polynomial X^{25}+X^{3}+X^{2}+X+1. The resulting sequences thus constitute segments of a set of Gold sequences.
The sequence c_{long,2,n} is a 16777232 chip shifted version of the sequence c_{long,1,n}.
Let n_{23} … n_{0 }be the 24 bit binary representation of the scrambling sequence number n with n_{0 }being the least significant bit. The x sequence depends on the chosen scrambling sequence number n and is denoted x_{n}, in the sequel. Furthermore, let x_{n}(i) and y(i) denote the i:th symbol of the sequence x_{n} and y, respectively.
The msequences x_{n} and y are constructed as:
Initial conditions:
– x_{n}(0)=n_{0} , x_{n}(1)= n_{1} , … =x_{n}(22)= n_{22} ,x_{n}(23)= n_{23}, x_{n}(24)=1.
– y(0)=y(1)= … =y(23)= y(24)=1.
Recursive definition of subsequent symbols:
– x_{n}(i+25) =x_{n}(i+3) + x_{n}(i) modulo 2, i=0,…, 2^{25}27.
– y(i+25) = y(i+3)+y(i+2) +y(i+1) +y(i) modulo 2, i=0,…, 2^{25}27.
Define the binary Gold sequence z_{n} by:
– z_{n}(i) = x_{n}(i) + y(i) modulo 2, i = 0, 1, 2, …, 2^{25}2.
The real valued Gold sequence Z_{n} is defined by:
Now, the realvalued long scrambling sequences c_{long,1,n} and c_{long,2,n} are defined as follows:
c_{long,1,n}(i) = Z_{n}(i), i = 0, 1, 2, …, 2^{25} – 2 and
c_{long,2,n}(i) = Z_{n}((i + 16777232) modulo (2^{25} – 1)), i = 0, 1, 2, …, 2^{25} – 2.
Finally, the complexvalued long scrambling sequence C_{long, n}, is defined as:
where i = 0, 1, …, 2^{25} – 2 and denotes rounding to nearest lower integer.
Figure 5: Configuration of uplink scrambling sequence generator
4.3.2.3 Short scrambling sequence
The short scrambling sequences c_{short,1,}_{n}(i) and c_{short,2,}_{n}(i) are defined from a sequence from the family of periodically extended S(2) codes.
Let n_{23}n_{22}…n_{0} be the 24 bit binary representation of the code number n.
The n:th quaternary S(2) sequence z_{n}(i), 0 £ n £ 16777215, is obtained by modulo 4 addition of three sequences, a quaternary sequence a(i) and two binary sequences b(i) and d(i), where the initial loading of the three sequences is determined from the code number n. The sequence z_{n}(i) of length 255 is generated according to the following relation:
– z_{n}(i) = a(i) + 2b(i) + 2d(i) modulo 4, i = 0, 1, …, 254;
where the quaternary sequence a(i) is generated recursively by the polynomial g_{0}(x)= x^{8}+3x^{5}+x^{3}+3x^{2}+2x+3 as:
– a(0) = 2n_{0} + 1 modulo 4;
– a(i) = 2n_{i} modulo 4, i = 1, 2, …, 7;
– a(i) = 3a(i3) + a(i5) + 3a(i6) + 2a(i7) + 3a(i8) modulo 4, i = 8, 9, …, 254;
and the binary sequence b(i) is generated recursively by the polynomial g_{1}(x)= x^{8}+x^{7}+x^{5}+x+1 as
b(i) = n_{8+}_{i} modulo 2, i = 0, 1, …, 7,
b(i) = b(i1) + b(i3) + b(i7) + b(i8) modulo 2, i = 8, 9, …, 254,
and the binary sequence d(i) is generated recursively by the polynomial g_{2}(x)= x^{8}+x^{7}+x^{5}+x^{4}+1 as:
d(i) = n_{16+}_{i} modulo 2, i = 0, 1, …, 7;
d(i) = d(i1) + d(i3) + d(i4) + d(i8) modulo 2, i = 8, 9, …, 254.
The sequence z_{n}(i) is extended to length 256 chips by setting z_{n}(255) = z_{n}(0).
The mapping from z_{n}(i) to the realvalued binary sequences c_{short,1,}_{n}(i) and c_{short,2,}_{n}(i), , i = 0, 1, …, 255 is defined in Table 2.
Table 2: Mapping from z_{n}(i) to c_{short,1,n}(i) and c_{short,2,n}(i), i = 0, 1, …, 255
z_{n}(i) 
c_{short,1,n}(i) 
c_{short,2,n}(i) 
0 
+1 
+1 
1 
1 
+1 
2 
1 
1 
3 
+1 
1 
Finally, the complexvalued short scrambling sequence C_{short, n}, is defined as:
where i = 0, 1, 2, … and denotes rounding to nearest lower integer.
An implementation of the short scrambling sequence generator for the 255 chip sequence to be extended by one chip is shown in Figure 6.
Figure 6: Uplink short scrambling sequence generator for 255 chip sequence
4.3.2.4 Dedicated physical channels scrambling code
The code used for scrambling of the uplink dedicated physical channels may be of either long or short type. The n:th uplink scrambling code, denoted S_{dpch, n}, is defined as:
S_{dpch,n}(i) = C_{long,n}(i), i = 0, 1, …, 38399, when using long scrambling codes;
where the lowest index corresponds to the chip transmitted first in time and C_{long,n} is defined in subclause 4.3.2.2.
The n:th uplink scrambling code, denoted S_{dpch, n}, is defined as:
S_{dpch,n}(i) = C_{short,n}(i), i = 0, 1, …, 38399, when using short scrambling codes;
where the lowest index corresponds to the chip transmitted first in time and C_{short,n} is defined in subclause 4.3.2.3.
4.3.2.5 PRACH message part scrambling code
The scrambling code used for the PRACH message part is 10 ms long, and there are 8192 different PRACH scrambling codes defined.
The n:th PRACH message part scrambling code, denoted S_{rmsg,n}, where n = 0, 1, …, 8191, is based on the long scrambling sequence and is defined as:
S_{rmsg,n}(i) = C_{long,n}(i + 4096), i = 0, 1, …, 38399
where the lowest index corresponds to the chip transmitted first in time and C_{long,n} is defined in subclause 4.3.2.2.
The message part scrambling code has a onetoone correspondence to the scrambling code used for the preamble part. For one PRACH, the same code number is used for both scrambling codes, i.e. if the PRACH preamble scrambling code used is S_{rpre,m} then the PRACH message part scrambling code is S_{rmsg,m}, where the number m is the same for both codes.
4.3.2.6 Void
4.3.2.7 Void
4.3.3 PRACH preamble codes
4.3.3.1 Preamble code construction
The random access preamble code C_{pre,n,} is a complex valued sequence. It is built from a preamble scrambling code S_{r‑pre,n} and a preamble signature C_{sig,s} as follows:
– C_{pre,n,s}(k) = S_{rpre,n}(k) C_{sig,s}(k) , k = 0, 1, 2, 3, …, 4095;
where k=0 corresponds to the chip transmitted first in time and S_{rpre,n} and C_{sig,s} are defined in 4.3.3.2 and 4.3.3.3 below respectively.
4.3.3.2 Preamble scrambling code
The scrambling code for the PRACH preamble part is constructed from the long scrambling sequences. There are 8192 PRACH preamble scrambling codes in total.
The n:th preamble scrambling code, n = 0, 1, …, 8191, is defined as:
S_{rpre,n}(i) = c_{long,1,n}(i), i = 0, 1, …, 4095;
where the sequence c_{long,1,n} is defined in subclause 4.3.2.2.
The 8192 PRACH preamble scrambling codes are divided into 512 groups with 16 codes in each group. There is a onetoone correspondence between the group of PRACH preamble scrambling codes in a cell and the primary scrambling code used in the downlink of the cell. The k:th PRACH preamble scrambling code within the cell with downlink primary scrambling code m, k = 0, 1, 2, …, 15 and m = 0, 1, 2, …, 511, is S_{rpre,n}(i) as defined above with n = 16m + k.
4.3.3.3 Preamble signature
The preamble signature corresponding to a signature s consists of 256 repetitions of a length 16 signature P_{s}(n), n=0…15. This is defined as follows:
– C_{sig,}_{s}(i) = P_{s}(i modulo 16), i = 0, 1, …, 4095.
The signature P_{s}(n) is from the set of 16 Hadamard codes of length 16. These are listed in table 3.
Table 3: Preamble signatures
Preamble 
Value of n 

0 
1 
2 
3 
4 
5 
6 
7 
8 
9 
10 
11 
12 
13 
14 
15 

P_{0}(n) 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
P_{1}(n) 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
P_{2}(n) 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
P_{3}(n) 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
P_{4}(n) 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
P_{5}(n) 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
P_{6}(n) 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
P_{7}(n) 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
P_{8}(n) 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
P_{9}(n) 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
P_{10}(n) 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
P_{11}(n) 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
P_{12}(n) 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
P_{13}(n) 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
P_{14}(n) 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
P_{15}(n) 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 
1 