4.3 Code generation and allocation
25.2133GPPRelease 17Spreading and modulation (FDD)TS
4.3.1 Channelisation codes
4.3.1.1 Code definition
The channelisation codes of figure 1 are Orthogonal Variable Spreading Factor (OVSF) codes that preserve the orthogonality between a user’s different physical channels. The OVSF codes can be defined using the code tree of figure 4.
Figure 4: Code-tree for generation of Orthogonal Variable Spreading Factor (OVSF) codes
In figure 4, the channelisation codes are uniquely described as Cch,SF,k, where SF is the spreading factor of the code and k is the code number, 0 k SF-1.
Each level in the code tree defines channelisation codes of length SF, corresponding to a spreading factor of SF in figure 4.
The generation method for the channelisation code is defined as:
,
The leftmost value in each channelisation code word corresponds to the chip transmitted first in time.
4.3.1.2 Code allocation for dedicated physical channels
NOTE: Although subclause 4.3.1.2 has been reorganized in this release, the spreading operation for DPCCH and DPDCH remains unchanged as compared to the previous release.
4.3.1.2.1 Code allocation for DPCCH/ S-DPCCH/DPDCH/DPCCH2
For the DPCCH, S-DPCCH and DPDCHs the following applies:
– The DPCCH shall always be spread by code cc = Cch,256,0.
– The S-DPCCH shall always be spread by code csc = Cch,256,31.
– The DPCCH2 shall be spread with code cc2 as specified in table 1C.5.
– When only one DPDCH is to be transmitted, DPDCH1 shall be spread by code cd,1 = Cch,SF,k where SF is the spreading factor of DPDCH1 and k= SF / 4.
– When more than one DPDCH is to be transmitted, all DPDCHs have spreading factors equal to 4. DPDCHn shall be spread by the the code cd,n = Cch,4,k , where k = 1 if n {1, 2}, k = 3 if n {3, 4}, and k = 2 if n {5, 6}.
Table 1C.5: Channelisation code of DPCCH2
|
Nmax-dpdch (as defined in subclause 4.2.1) |
Channelisation code cc2 |
|
0 |
Cch,256,34 |
|
≥1 |
Cch,256,3 |
If a power control preamble is used to initialise a DCH, the channelisation code for the DPCCH during the power control preamble shall be the same as that to be used afterwards.
4.3.1.2.2 Code allocation for HS-DPCCH when the UE is not configured in MIMO mode with four transmit antennas in any cell
The HS-DPCCH shall be spread with code chs as specified in table 1D. If Secondary_Cell_Enabled is greater than 3 HS-DPCCH2 shall be spread with code chs as specified in table 1D.1.
If Secondary_Cell_Enabled as defined in [6] is 0 or 1 or if Secondary_Cell_Enabled is 2 and MIMO is not configured in any cell, HS-DPCCH slot format #0 as defined in [2] is used.
If Secondary_Cell_Enabled is 2 and MIMO is configured in at least one cell or if Secondary_Cell_Enabled is 3, HS-DPCCH slot format #1 as defined in [2] is used.
If Secondary_Cell_Enabled is greater than 3, HS-DPCCH slot format #1 as defined in [2] is used.
Table 1D: channelisation code of HS-DPCCH
|
Nmax-dpdch (as defined in subclause 4.2.1) |
Channelisation code chs |
||
|
Secondary_Cell_Enabled is 0, 1, 2 or 3 |
Secondary_Cell_Enabled is greater than 3 |
||
|
HS-DPCCH slot format #0 [2] |
HS-DPCCH slot format #1 [2] |
HS-DPCCH slot format #1 [2] |
|
|
0 |
C ch,256,33 |
C ch,128,16 |
C ch,128,16 |
|
1 |
Cch,256,64 |
C ch,128,32 |
C ch,128,16 |
|
2,4,6 |
Cch,256,1 |
N/A |
N/A |
|
3,5 |
Cch,256,32 |
N/A |
N/A |
Table 1D.1: channelisation code of HS-DPCCH2 if Secondary_Cell_Enabled is greater than 3.
|
Nmax-dpdch (as defined in subclause 4.2.1) |
Channelisation code chs |
|
Secondary_Cell_Enabled is greater than 3 |
|
|
HS-DPCCH slot format #1 [2] |
|
|
0 |
C ch,128,16 |
|
1 |
C ch,128,16 |
4.3.1.2.2A Code allocation for HS-DPCCH when the UE is configured in MIMO mode with four transmit antennas in at least one cell
If Secondary_Cell_Enabled as defined in [6] is 0 or 1, HS-DPCCH slot format #1 as defined in [2] is used. HS-DPCCH shall be spread with code chs as specified in table 1D.2.
If Secondary_Cell_Enabled is 2:
– If the UE is configured in MIMO mode with four transmit antennas in all cells, HS-DPCCH slot format #1 as defined in [2] is used for both HS-DPCCH and HS-DPCCH2. HS-DPCCH shall be spread with code chs as specified in table 1D.2 and HS-DPCCH2 spread with code chs as specified in table 1D.3.
– If the number of cells configured in MIMO mode with four transmit antennas is less than 3 and if the UE is configured in MIMO mode with four transmit antennas either in the primary or in the 1st secondary serving cell or both, then HS-DPCCH slot format #1 as defined in [2] is used for HS-DPCCH. HS-DPCCH shall be spread with code chs as specified in table 1D.2.
– If the number of cells configured in MIMO mode with four transmit antennas is less than 3 and if the UE is not configured in MIMO mode with four transmit antennas in the primary and the 1st secondary serving cell then HS-DPCCH slot format #0 as defined in [2] is used for HS-DPCCH. HS-DPCCH shall be spread with code chs as specified in table 1D.4.
– If the number of cells configured in MIMO mode with four transmit antennas is less than 3 and if the UE is configured in MIMO mode with four transmit antennas in the 2nd secondary serving cell then HS-DPCCH slot format #1 as defined in [2] is used for HS-DPCCH2. HS-DPCCH2 spread with code chs as specified in table 1D.3.
– If the number of cells configured in MIMO mode with four transmit antennas is less than 3 and if the UE is not configured in MIMO mode with four transmit antennas in the 2nd secondary serving cell then HS-DPCCH slot format #0 as defined in [2] is used for HS-DPCCH2. HS-DPCCH2 spread with code chs as specified in table 1D.5.
If Secondary_Cell_Enabled is 3:
– If the UE is configured in MIMO mode with four transmit antennas in more than 2 cells HS-DPCCH slot format #1 as defined in [2] is used for both HS-DPCCH and HS-DPCCH2. HS-DPCCH shall be spread with code chs as specified in table 1D.2 and HS-DPCCH2 spread with code chs as specified in table 1D.3.
– If the number of cells configured in MIMO mode with four transmit antennas is less than 3 and if the UE is configured in MIMO mode with four transmit antennas either in the primary or in the 1st secondary serving cell or both, then HS-DPCCH slot format #1 as defined in [2] is used for HS-DPCCH. HS-DPCCH shall be spread with code chs as specified in table 1D.2.
– If the number of cells configured in MIMO mode with four transmit antennas is less than 3 and if the UE is not configured in MIMO mode with four transmit antennas in the primary and the 1st secondary serving cell then HS-DPCCH slot format #0 as defined in [2] is used for HS-DPCCH. HS-DPCCH shall be spread with code chs as specified in table 1D.4.
– If the number of cells configured in MIMO mode with four transmit antennas is less than 3 and if the UE is configured in MIMO mode with four transmit antennas in the 2nd serving or in the 3rd serving secondary cell or both then HS-DPCCH slot format #1 as defined in [2] is used for HS-DPCCH2. HS-DPCCH2 spread with code chs as specified in table 1D.3.
– If the number of cells configured in MIMO mode with four transmit antennas is less than 3 and if the UE is not configured in MIMO mode with four transmit antennas in the 2nd and the 3rd secondary serving cell then HS-DPCCH slot format #0 as defined in [2] is used for HS-DPCCH2. HS-DPCCH2 spread with code chs as specified in table 1D.5.
Table 1D.2: channelisation code of HS-DPCCH if Secondary_Cell_Enabled is 0 or 1 or 2 or 3 and the UE is configured in MIMO mode with four transmit antennas in any cell
|
Nmax-dpdch (as defined in subclause 4.2.1) |
Channelisation code chs, Secondary_Cell_Enabled is 0, 1 |
Channelisation code chs, Secondary_Cell_Enabled is 2, 3 |
|
HS-DPCCH slot format #1 [2] |
HS-DPCCH slot format #1 [2] |
|
|
0 |
Cch,128,16 |
Cch,128,16 |
|
1 |
Cch,128,32 |
Cch,128,16 |
Table 1D.3: channelisation code of HS-DPCCH2 if Secondary_Cell_Enabled is 2 or 3 and the UE is configured in MIMO mode with four transmit antennas in any cell
|
Nmax-dpdch (as defined in subclause 4.2.1) |
Channelisation code chs |
Channelisation code chs |
|
HS-DPCCH slot format #0 [2] |
HS-DPCCH slot format #1 [2] |
|
|
0 |
Cch,256,32 |
Cch,128,16 |
|
1 |
Cch,256,32 |
Cch,128,16 |
Table 1D.4: channelisation code of HS-DPCCH if Secondary_Cell_Enabled is greater than 1 and the UE is not configured in MIMO mode with four transmit antennas in the primary and the 1st secondary serving cell.
|
Nmax-dpdch (as defined in subclause 4.2.1) |
Channelisation code chs |
|
Secondary_Cell_Enabled is greater than 1 |
|
|
HS-DPCCH slot format #0 [2] |
|
|
0 |
C ch,256,33 |
|
1 |
C ch,256,64 |
Table 1D.5: channelisation code of HS-DPCCH2 if Secondary_Cell_Enabled is equal to 3 and the UE is not configured in MIMO mode with four transmit antennas in the 2nd and the 3rd secondary serving cell or if Secondary_Cell_Enabled is equal to 2 and the UE is not configured in MIMO mode with four transmit antennas in the 2nd secondary serving cell.
|
Nmax-dpdch (as defined in subclause 4.2.1) |
Channelisation code chs |
|
Secondary_Cell_Enabled is greater than 1 |
|
|
HS-DPCCH slot format #0 [2] |
|
|
0 |
C ch,256,33 |
|
1 |
C ch,256,64 |
4.3.1.2.3 Code allocation for E-DPCCH/E-DPDCH
The E-DPCCH shall be spread with channelisation code cec = Cch,256,1.
E-DPDCHk shall be spread with channelisation code ced,k. The sequence ced,k depends on Nmax-dpdch and the spreading factor selected for the corresponding frame or sub-frame as specified in [7]; it shall be selected according to table 1E.
Table 1E: Channelisation code for E-DPDCH
|
Nmax-dpdch |
E-DPDCHk |
Channelisation code Ced,k |
|
0 |
E-DPDCH1 |
Cch,SF,SF/4 if SF 4 Cch,2,1 if SF = 2 |
|
E-DPDCH2 |
Cch,4,1 if SF = 4 Cch,2,1 if SF = 2 |
|
|
E-DPDCH3 E-DPDCH4 |
Cch,4,1 |
|
|
1 |
E-DPDCH1 |
Cch,SF,SF/2 |
|
E-DPDCH2 |
Cch,4,2 if SF = 4 Cch,2,1 if SF = 2 |
NOTE: When more than one E-DPDCH is transmitted, the respective channelisation codes used for E-DPDCH1 and E-DPDCH2 are always the same.
4.3.1.2.4 Code allocation for S-E-DPCCH/S-E-DPDCH
The S-E-DPCCH shall be spread with channelisation code csec = Cch,256,1.
S-E-DPDCHk shall be spread with channelisation code csed,k. The sequence csed,k shall be selected according to table 1F.
Table 1F: Channelisation code for S-E-DPDCH
|
Nmax-dpdch |
S-E-DPDCHk |
Channelisation code Csed,k |
|
0 |
S-E-DPDCH1 S-E-DPDCH2 |
Cch,2,1 |
|
S-E-DPDCH3 S-E-DPDCH4 |
Cch,4,1 |
NOTE: Either none or all four S-E-DPDCHs are transmitted.
4.3.1.3 Code allocation for PRACH message part
The preamble signature s, 0 s 15, points to one of the 16 nodes in the code-tree that corresponds to channelisation codes of length 16. The sub-tree below the specified node is used for spreading of the message part. The control part is spread with the channelisation code cc (as shown in subclause 4.2.2.2) of spreading factor 256 in the lowest branch of the sub-tree, i.e. cc = Cch,256,m where m = 16s + 15. The data part uses any of the channelisation codes from spreading factor 32 to 256 in the upper-most branch of the sub-tree. To be exact, the data part is spread by channelisation code cd = Cch,SF,m and SF is the spreading factor used for the data part and m = SFs/16.
4.3.1.4 Void
4.3.1.5 Void
4.3.2 Scrambling codes
4.3.2.1 General
All uplink physical channels on an activated uplink frequency shall be scrambled with a complex-valued scrambling code. The dedicated physical channels may be scrambled by either a long or a short scrambling code, defined in subclause 4.3.2.4. The PRACH message part shall be scrambled with a long scrambling code, defined in subclause 4.3.2.5. There are 224 long and 224 short uplink scrambling codes. Uplink scrambling codes are assigned by higher layers.
The long scrambling code is built from constituent long sequences defined in subclause 4.3.2.2, while the constituent short sequences used to build the short scrambling code are defined in subclause 4.3.2.3.
4.3.2.2 Long scrambling sequence
The long scrambling sequences clong,1,n and clong,2,n are constructed from position wise modulo 2 sum of 38400 chip segments of two binary m-sequences generated by means of two generator polynomials of degree 25. Let x, and y be the two m-sequences respectively. The x sequence is constructed using the primitive (over GF(2)) polynomial X25+X3+1. The y sequence is constructed using the polynomial X25+X3+X2+X+1. The resulting sequences thus constitute segments of a set of Gold sequences.
The sequence clong,2,n is a 16777232 chip shifted version of the sequence clong,1,n.
Let n23 … n0 be the 24 bit binary representation of the scrambling sequence number n with n0 being the least significant bit. The x sequence depends on the chosen scrambling sequence number n and is denoted xn, in the sequel. Furthermore, let xn(i) and y(i) denote the i:th symbol of the sequence xn and y, respectively.
The m-sequences xn and y are constructed as:
Initial conditions:
– xn(0)=n0 , xn(1)= n1 , … =xn(22)= n22 ,xn(23)= n23, xn(24)=1.
– y(0)=y(1)= … =y(23)= y(24)=1.
Recursive definition of subsequent symbols:
– xn(i+25) =xn(i+3) + xn(i) modulo 2, i=0,…, 225-27.
– y(i+25) = y(i+3)+y(i+2) +y(i+1) +y(i) modulo 2, i=0,…, 225-27.
Define the binary Gold sequence zn by:
– zn(i) = xn(i) + y(i) modulo 2, i = 0, 1, 2, …, 225-2.
The real valued Gold sequence Zn is defined by:
Now, the real-valued long scrambling sequences clong,1,n and clong,2,n are defined as follows:
clong,1,n(i) = Zn(i), i = 0, 1, 2, …, 225 – 2 and
clong,2,n(i) = Zn((i + 16777232) modulo (225 – 1)), i = 0, 1, 2, …, 225 – 2.
Finally, the complex-valued long scrambling sequence Clong, n, is defined as:
where i = 0, 1, …, 225 – 2 and denotes rounding to nearest lower integer.
Figure 5: Configuration of uplink scrambling sequence generator
4.3.2.3 Short scrambling sequence
The short scrambling sequences cshort,1,n(i) and cshort,2,n(i) are defined from a sequence from the family of periodically extended S(2) codes.
Let n23n22…n0 be the 24 bit binary representation of the code number n.
The n:th quaternary S(2) sequence zn(i), 0 £ n £ 16777215, is obtained by modulo 4 addition of three sequences, a quaternary sequence a(i) and two binary sequences b(i) and d(i), where the initial loading of the three sequences is determined from the code number n. The sequence zn(i) of length 255 is generated according to the following relation:
– zn(i) = a(i) + 2b(i) + 2d(i) modulo 4, i = 0, 1, …, 254;
where the quaternary sequence a(i) is generated recursively by the polynomial g0(x)= x8+3x5+x3+3x2+2x+3 as:
– a(0) = 2n0 + 1 modulo 4;
– a(i) = 2ni modulo 4, i = 1, 2, …, 7;
– a(i) = 3a(i-3) + a(i-5) + 3a(i-6) + 2a(i-7) + 3a(i-8) modulo 4, i = 8, 9, …, 254;
and the binary sequence b(i) is generated recursively by the polynomial g1(x)= x8+x7+x5+x+1 as
b(i) = n8+i modulo 2, i = 0, 1, …, 7,
b(i) = b(i-1) + b(i-3) + b(i-7) + b(i-8) modulo 2, i = 8, 9, …, 254,
and the binary sequence d(i) is generated recursively by the polynomial g2(x)= x8+x7+x5+x4+1 as:
d(i) = n16+i modulo 2, i = 0, 1, …, 7;
d(i) = d(i-1) + d(i-3) + d(i-4) + d(i-8) modulo 2, i = 8, 9, …, 254.
The sequence zn(i) is extended to length 256 chips by setting zn(255) = zn(0).
The mapping from zn(i) to the real-valued binary sequences cshort,1,n(i) and cshort,2,n(i), , i = 0, 1, …, 255 is defined in Table 2.
Table 2: Mapping from zn(i) to cshort,1,n(i) and cshort,2,n(i), i = 0, 1, …, 255
|
zn(i) |
cshort,1,n(i) |
cshort,2,n(i) |
|
0 |
+1 |
+1 |
|
1 |
-1 |
+1 |
|
2 |
-1 |
-1 |
|
3 |
+1 |
-1 |
Finally, the complex-valued short scrambling sequence Cshort, n, is defined as:
where i = 0, 1, 2, … and denotes rounding to nearest lower integer.
An implementation of the short scrambling sequence generator for the 255 chip sequence to be extended by one chip is shown in Figure 6.
Figure 6: Uplink short scrambling sequence generator for 255 chip sequence
4.3.2.4 Dedicated physical channels scrambling code
The code used for scrambling of the uplink dedicated physical channels may be of either long or short type. The n:th uplink scrambling code, denoted Sdpch, n, is defined as:
Sdpch,n(i) = Clong,n(i), i = 0, 1, …, 38399, when using long scrambling codes;
where the lowest index corresponds to the chip transmitted first in time and Clong,n is defined in subclause 4.3.2.2.
The n:th uplink scrambling code, denoted Sdpch, n, is defined as:
Sdpch,n(i) = Cshort,n(i), i = 0, 1, …, 38399, when using short scrambling codes;
where the lowest index corresponds to the chip transmitted first in time and Cshort,n is defined in subclause 4.3.2.3.
4.3.2.5 PRACH message part scrambling code
The scrambling code used for the PRACH message part is 10 ms long, and there are 8192 different PRACH scrambling codes defined.
The n:th PRACH message part scrambling code, denoted Sr-msg,n, where n = 0, 1, …, 8191, is based on the long scrambling sequence and is defined as:
Sr-msg,n(i) = Clong,n(i + 4096), i = 0, 1, …, 38399
where the lowest index corresponds to the chip transmitted first in time and Clong,n is defined in subclause 4.3.2.2.
The message part scrambling code has a one-to-one correspondence to the scrambling code used for the preamble part. For one PRACH, the same code number is used for both scrambling codes, i.e. if the PRACH preamble scrambling code used is Sr-pre,m then the PRACH message part scrambling code is Sr-msg,m, where the number m is the same for both codes.
4.3.2.6 Void
4.3.2.7 Void
4.3.3 PRACH preamble codes
4.3.3.1 Preamble code construction
The random access preamble code Cpre,n, is a complex valued sequence. It is built from a preamble scrambling code Sr‑pre,n and a preamble signature Csig,s as follows:
– Cpre,n,s(k) = Sr-pre,n(k) Csig,s(k) , k = 0, 1, 2, 3, …, 4095;
where k=0 corresponds to the chip transmitted first in time and Sr-pre,n and Csig,s are defined in 4.3.3.2 and 4.3.3.3 below respectively.
4.3.3.2 Preamble scrambling code
The scrambling code for the PRACH preamble part is constructed from the long scrambling sequences. There are 8192 PRACH preamble scrambling codes in total.
The n:th preamble scrambling code, n = 0, 1, …, 8191, is defined as:
Sr-pre,n(i) = clong,1,n(i), i = 0, 1, …, 4095;
where the sequence clong,1,n is defined in subclause 4.3.2.2.
The 8192 PRACH preamble scrambling codes are divided into 512 groups with 16 codes in each group. There is a one-to-one correspondence between the group of PRACH preamble scrambling codes in a cell and the primary scrambling code used in the downlink of the cell. The k:th PRACH preamble scrambling code within the cell with downlink primary scrambling code m, k = 0, 1, 2, …, 15 and m = 0, 1, 2, …, 511, is Sr-pre,n(i) as defined above with n = 16m + k.
4.3.3.3 Preamble signature
The preamble signature corresponding to a signature s consists of 256 repetitions of a length 16 signature Ps(n), n=0…15. This is defined as follows:
– Csig,s(i) = Ps(i modulo 16), i = 0, 1, …, 4095.
The signature Ps(n) is from the set of 16 Hadamard codes of length 16. These are listed in table 3.
Table 3: Preamble signatures
|
Preamble |
Value of n |
|||||||||||||||
|
0 |
1 |
2 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
10 |
11 |
12 |
13 |
14 |
15 |
|
|
P0(n) |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
|
P1(n) |
1 |
-1 |
1 |
-1 |
1 |
-1 |
1 |
-1 |
1 |
-1 |
1 |
-1 |
1 |
-1 |
1 |
-1 |
|
P2(n) |
1 |
1 |
-1 |
-1 |
1 |
1 |
-1 |
-1 |
1 |
1 |
-1 |
-1 |
1 |
1 |
-1 |
-1 |
|
P3(n) |
1 |
-1 |
-1 |
1 |
1 |
-1 |
-1 |
1 |
1 |
-1 |
-1 |
1 |
1 |
-1 |
-1 |
1 |
|
P4(n) |
1 |
1 |
1 |
1 |
-1 |
-1 |
-1 |
-1 |
1 |
1 |
1 |
1 |
-1 |
-1 |
-1 |
-1 |
|
P5(n) |
1 |
-1 |
1 |
-1 |
-1 |
1 |
-1 |
1 |
1 |
-1 |
1 |
-1 |
-1 |
1 |
-1 |
1 |
|
P6(n) |
1 |
1 |
-1 |
-1 |
-1 |
-1 |
1 |
1 |
1 |
1 |
-1 |
-1 |
-1 |
-1 |
1 |
1 |
|
P7(n) |
1 |
-1 |
-1 |
1 |
-1 |
1 |
1 |
-1 |
1 |
-1 |
-1 |
1 |
-1 |
1 |
1 |
-1 |
|
P8(n) |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
-1 |
-1 |
-1 |
-1 |
-1 |
-1 |
-1 |
-1 |
|
P9(n) |
1 |
-1 |
1 |
-1 |
1 |
-1 |
1 |
-1 |
-1 |
1 |
-1 |
1 |
-1 |
1 |
-1 |
1 |
|
P10(n) |
1 |
1 |
-1 |
-1 |
1 |
1 |
-1 |
-1 |
-1 |
-1 |
1 |
1 |
-1 |
-1 |
1 |
1 |
|
P11(n) |
1 |
-1 |
-1 |
1 |
1 |
-1 |
-1 |
1 |
-1 |
1 |
1 |
-1 |
-1 |
1 |
1 |
-1 |
|
P12(n) |
1 |
1 |
1 |
1 |
-1 |
-1 |
-1 |
-1 |
-1 |
-1 |
-1 |
-1 |
1 |
1 |
1 |
1 |
|
P13(n) |
1 |
-1 |
1 |
-1 |
-1 |
1 |
-1 |
1 |
-1 |
1 |
-1 |
1 |
1 |
-1 |
1 |
-1 |
|
P14(n) |
1 |
1 |
-1 |
-1 |
-1 |
-1 |
1 |
1 |
-1 |
-1 |
1 |
1 |
1 |
1 |
-1 |
-1 |
|
P15(n) |
1 |
-1 |
-1 |
1 |
-1 |
1 |
1 |
-1 |
-1 |
1 |
1 |
-1 |
1 |
-1 |
-1 |
1 |