7 Timing characteristics
25.1233GPPRelease 17Requirements for support of radio resource management (TDD)TS
7.1 Timing Advance
7.1.1 3.84 Mcps TDD option
7.1.1.1 Introduction
The timing advance is initiated from UTRAN with an RRC message that implies an adjustement of the timing advance, see TS 25.331 section 8.6.6.26.
To update timing advance of a UE, the UTRAN measures RX Timing deviation. The measurements are defined in TS 25.225 and measurement accuracies are specified in section 9.
7.1.1.2 Requirements
7.1.1.2.1 Timing Advance adjustment accuracy
The UE shall adjust the timing of its transmissions with an accuracy better than or equal to ±0.5 chip to the signalled timing advance value.
7.1.1.2.2 Timing Advance adjustment delay
The UE shall adjust the timing of its transmission at the designated activation time, when the indicated activation time is later than DTA msec from the end of the last TTI containing the RRC message implying an adjustment of the timing advance.
DTA equals the RRC procedure delay of the RRC message implying an adjustment of the timing advance as defined in TS25.331 section 13.5.
7.1.2 1.28 Mcps TDD option
For 1.28 Mcps TDD the timing advance in the UE is adjusted by means of uplink synchronization. For the random access procedure the node B commands the UE to adjust its synchronisation shift by means of signalling the received position of the UpPTS in the FPACH. During the connection the node B measures the timing in the uplink and transmits a SS (Synchronization Shift) command to the UE at least once per sub-frame.
These SS commands determined whether the UE synchronization shift is either left unchanged, or adjusted 1 step up or 1 step down. The step size of the SS adjustment is (k/8)Tc where k (=1,2, …,8) is signalled by higher layer signalling.
7.1.2.1 Uplink synchronization control requirements for UE for 1.28 Mcps TDD option
Uplink synchronization control is the ability of the UE transmitter to adjust its TX timing in accordance with one or more SS commands received in the downlink.
7.1.2.1.1 Uplink synchronization control steps
The SS step is the change in UE transmission timing in response to a single SS command, SS_cmd, received by the UE.
7.1.2.1.1.1 Minimum requirement
The UE transmitter shall have the capability of changing the transmission timing with a step size of 1/8, 2/8, 3/8, …, 1 chip according to the value of Δ SS, within n=(1,2,…,6) time slots excluding special timeslots (DwPTS, GP, UpPTS) after the SS_cmd arrived (closed loop). For the open loop any step being a multiple of 1/8 chip has to be allowed.
a) The minimum transmission timing step Δ SS,min due to closed loop uplink synchronization control shall be within the range shown in Table 7.1.
b) In case uplink synchronization control implies larger adjustment than the minimum step the UE shall perform a multiple integer number of the minimum step. Within the implementation grid of the applicable timing steps of the UE the step being closest to the required step should be executed.
Table 7.1: Uplink synchronisation control range
SS_cmd |
Uplink synchronisation control range for minimum step |
|
1/8 chip step size |
||
Lower |
Upper |
|
Up |
1/9 chip |
1/7 chip |
Down |
1/9 chip |
1/7 chip |
7.1.3 7.68 Mcps TDD option
7.1.3.1 Introduction
The timing advance is initiated from UTRAN with an RRC message that implies an adjustement of the timing advance, see TS 25.331 section 8.6.6.26.
To update timing advance of a UE, the UTRAN measures RX Timing deviation. The measurements are defined in TS 25.225 and measurement accuracies are specified in section 9.
7.1.3.2 Requirements
7.1.3.2.1 Timing Advance adjustment accuracy
The UE shall adjust the timing of its transmissions with an accuracy better than or equal to ±0.5 chip to the signalled timing advance value.
7.1.3.2.2 Timing Advance adjustment delay
The UE shall adjust the timing of its transmission at the designated activation time, when the indicated activation time is later than DTA msec from the end of the last TTI containing the RRC message implying an adjustment of the timing advance.
DTA equals the RRC procedure delay of the RRC message implying an adjustment of the timing advance as defined in TS25.331 section 13.5.
7.2 Cell synchronization accuracy
7.2.1 Definition
Cell synchronization accuracy is defined as the maximum deviation in frame start times between any pair of cells on the same frequency that have overlapping coverage areas.
7.2.2 Minimum requirements
The cell synchronization accuracy shall be better than or equal to 3μs.
7.3 UE Transmit Timing for 3.84 Mcps TDD Option
7.3.1 Definition
UE transmit timing is defined as the frame start time of uplink transmissions relative to the downlink frame timing at zero propagation delay with timing advance turned off. The reference point for UE transmit timing shall be the antenna connector. This is applicable for the AWGN propagation condition. In the case of multi-path fading conditions, the reference point for UE transmit timing shall be the first significant path of the received PCCPCH.
7.3.2 Minimum Requirement
The UE transmit timing error shall be within 0 to +3 chips for the AWGN propagation condition.
7.3A UE Transmit Timing for 7.68 Mcps TDD Option
7.3A.1 Definition
UE transmit timing is defined as the frame start time of uplink transmissions relative to the downlink frame timing at zero propagation delay with timing advance turned off. The reference point for UE transmit timing shall be the antenna connector. This is applicable for the AWGN propagation condition. In the case of multi-path fading conditions, the reference point for UE transmit timing shall be the first significant path of the received PCCPCH.
7.3A.2 Minimum Requirement
The UE transmit timing error shall be within 0 to +3 chips for the AWGN propagation condition.
7.4 UE timer accuracy
7.4.1 Introduction
UE timers are used in different protocol entities to control the UE behaviour.
7.4.2 Requirements
For UE timers T3xx, Tbarred, Treselection, Penalty_time, TCRmax, TCrmaxHyst [16], UE shall comply with the timer accuracies according to Table 7.2.
The requirements are only related to the actual timing measurements internally in the UE. They do not include the following:
– Inaccuracy in the start and stop conditions of a timer (e.g. UE reaction time to detect that start and stop conditions of a timer is fulfilled), or
– Inaccuracies due to restrictions in observability of start and stop conditions of a UE timer (e.g. TTI alignment when UE sends messages at timer expiry).
Table 7.2
Timer value [s] |
Accuracy |
timer value <4 |
± 0.1 s |
timer value ≥ 4 |
± 2.5 % |
7.5 UE Uplink Synchronization
7.5.1 3.84 Mcps TDD option
Void.
7.5.2 1.28 Mcps TDD option
7.5.2.1 Uplink synchronization control for PRACH
7.5.2.1.1 Introduction
The establishment of uplink synchronization is done during the random access procedure and involves the UpPCH and the PRACH. To update timing advance of a UE, the UTRAN measures SYNC-UL Timing deviation. Uplink synchronization control for PRACH is used to adjust its synchronisation shift by means of signalling the received position of the UpPTS in the FPACH.
Time of the beginning of the PRACH TTX‑PRACH is given by:
TTX-PRACH = TRX-PRACH – (UpPCHADV + UpPCHPOS – 8*16 TC)
in multiple of 1/8 chips, where
TTX-PRACH is the beginning time of PRACH transmission with the UE’s timing,
TRX-PRACH is the beginning time of PRACH reception with the UE’s timing if the PRACH was a DL channel.
UpPCHPOS is the received SYNC-UL timing deviation measured by UTRAN.
UpPCHADV is the timing advance of SYNC-UL given by UE.
Then the timing advance for PRACH is given by:
TADV-PRACH = TRX-PRACH – TTX-PRACH = (UpPCHADV + UpPCHPOS – 8*16 TC)
The procedure and measurements are defined in TS 25.224 section 5.2.2 and section 5.2.3.
7.5.2.1.2 Requirements
The uplink synchronization accuracy for PRACH is defined as PRACH timing deviation between received PRACH position and desired PRACH position. The accuracy requirements of uplink synchronization control for PRACH are decided by the accuracy of UpPCH timing advance UpPCHADV measured by UE and the accuracy of SYNC-UL timing deviation UpPCHPOS measured by UTRAN, which refer to section 9.1.2.2 and section 9.2.1.10.
Table 7.3: Uplink synchronisation control accuracy requirements
Parameter |
Unit |
Accuracy [chip] |
Conditions |
Io [dBm/ 1.28 MHz] |
|||
Uplink synchronization control for PRACH |
chip |
+/- 0.5 |
-94…-50 |
7.5.2.2 Uplink synchronization control during handover
7.5.2.2.1 Introduction
The closed loop uplink synchronisation control uses layer 1 symbols (SS commands) for DPCH and PUSCH. After establishment of the uplink synchronisation, NodeB and UE start to use the closed loop UL synchronisation control procedure. This procedure is continuous during connected mode.
During a 1.28 Mcps TDD to 1.28 Mcps TDD hand-over the UE shall transmit in the new cell with timing advance TA adjusted by the relative timing difference Δt between the new and the old cell if indicated by higher layers:
TAnew = TAold + 2Δt.
TAnew is the timing advance of the new cell.
TAold is the timing advance of the old cell,
Δt is the relative timing difference between the new and the old cell, which is measured by UE as SFN-SFN observed time difference type 2.
7.5.2.2.2 Requirements
The uplink synchronization accuracy during handover is defined as timing deviation between the initial actual uplink synchronization position and the desired position of the first uplink DPCH on the target cell. The accuracy requirements of uplink synchronization control during handover are decided by the accuracy of the timing advance and the accuracy of SFN-SFN observed time difference type 2 measured by UE, which refer to section 9.1.1.8 and section 9.1.2.2.
Table 7.4: Uplink synchronisation control accuracy requirements
Parameter |
Unit |
Accuracy [chip] |
Conditions |
Io [dBm/ 1.28 MHz] |
|||
Uplink synchronization control during handover |
chip |
+/- 0.5 |
-94…-50 |
7.5.3 7.68 Mcps TDD option
Void.