N.1 Interferer configurations

3GPP45.005GSM/EDGE Radio transmission and receptionTS

In all reference DARP Test Scenarios (DTS), the wanted signal shall always use Training Sequence (TSC) 0.

In each reference Test Scenario, the co-channel and adjacent channel interferers are GMSK modulated, except for DTS-1b where the cochannnel interferer is 8-PSK modulated. The power of the interferers is measured before any receiver filtering and during the active part of the desired burst (see 3GPP TS 45.004). No Training Sequence Code (TSC) is used, and thus the midamble is filled with random data bits.

In some test scenarios an AWGN source is added to the interferers. The AWGN power is measured over a bandwidth of 270,833 kHz.

All power levels are relative to the signal level of the strongest co-channel interferer.

Power ramping according to the requirements in 3GPP TS 45.005 shall be applied to all delayed interferers. The other interferers shall be random, continuous GMSK-modulated signals.

NOTE: The non-delayed interferer is the same signal for which reference interference performance requirements normally apply (see clause 6.3).

In adjacent timeslots of the delayed interferers no power shall be applied.

The level of the strongest co-channel interferer (Co-channel 1) shall be -70 dBm.

The delay is measured from the same bit position in the wanted signal burst and the interferer burst, where the position in the wanted signal is the reference position.

Table N.1-1 Reference Test Scenario for synchronous single co-channel interferer

Reference Test Scenario	Interfering Signal	Interferer relative power level	TSC	Interferer Delay range
DTS-1	Co-channel 1	0 dB	none	no delay
DTS-1b	Co-channel 1 8PSK	0 dB	none	no delay

Table N.1-2 Reference Test Scenarios for synchronous multiple interferers

Reference Test Scenario	Interfering Signal	Interferer relative power level	TSC	Interferer Delay range
DTS-2	Co-channel 1 Co-channel 2 Adjacent 1 AWGN	0 dB -10 dB 3 dB -17 dB	none none none –	no delay no delay no delay –

Table N.1-3 Reference Test Scenario for asynchronous multiple interferers

Reference Test Scenario	Interfering Signal	Interferer relative power level	TSC	Interferer Delay
DTS-5	Co-channel 1 Co-channel 2 Adjacent 1 AWGN	0 dB *) -10 dB 3 dB -17 dB	none none none –	74 symbols no delay no delay –
*) The power of the delayed interferer burst, averaged over the active part of the wanted signal burst. The power of the delayed interferer burst, averaged over the active part of the delayed interferer burst is 3 dB higher.