C.3.2 Power Delay Profile (PDP)

38.1513GPPNRRelease 17TSUser Equipment (UE) Multiple Input Multiple Output (MIMO) Over-the-Air (OTA) performance requirements

This measurement checks that the resulting power delay profile (PDP) is in-line with the PDP defined for the channel model. For PDP validation measurement, only Vertical validation is required.

The PDP measurement is performed with a Vector Network Analyser (VNA). An example setup for PDP measurement is shown in Figure C.3.2-1. VNA transmits frequency sweep signals thorough the NR MIMO OTA test system. A reference antenna (i.e dipole antenna), within the centre of the test zone, receives the signal and VNA analyses the frequency response of the system. A number of traces (frequency responses) are measured and recorded by VNA and analysed by a post processing SW, e.g., Matlab. Special care has to be taken into account to keep the fading conditions unchanged, i.e. frozen, during the short period of time of a single trace measurement. The fading may proceed only in between traces.

Figure C.3.2-1: Setup for PDP measurements

Step the emulation and store traces from VNA, i.e., run the emulation to CIR number 1, pause, measure VNA trace, run the emulation to CIR number 10, pause, measure VNA trace. Continue until 1000 VNA traces are measured.

VNA settings:

Table C.3.2-1: VNA settings for PDP measurements

Item	Unit	Value
Centre frequency	MHz	Downlink centre frequency in Table C.3.1-1
Span	MHz	200
Number of traces		1000
Number of points		1101
Averaging		1

Channel model specification:

Table C.3.2-2: Channel model specification for PDP measurements

Item	Unit	Value
Centre frequency	MHz	Downlink centre frequency in Table C.3.1-1
Distance between traces in channel model	wavelength (Note)	> 2
Channel model		As specified in Annex C.1
NOTE: Time [s] = distance [λ] / MS speed [λ/s] MS speed [λ/s] = MS speed [m/s] / Speed of light [m/s] * Centre frequency [Hz]

Method of measurement result analysis:

Measured VNA traces (frequency responses H(t,f)) are saved into a hard drive. The data is read into, e.g., Matlab.
The analysis is performed by taking the Fourier transform of each FR. The resulting impulse responses h(t,) are averaged in power over time:

Finally the resulting PDP is shifted in delay, such that the first tap is on delay zero.

Beam-Specific Block Diagram

It is assumed that the beams are mapped to the inputs of the channel emulator as follows:

– Beam 1: Input 1 and Input 2

– Beam 2: Input 3 and Input 4 (CDL-C UMa only)

Figure C.3.2-2: Setup for Beam-Specific PDP measurements (Beam 1)

Figure C.3.2-3: Setup for Beam-Specific PDP measurements (Beam 2 CDL-C UMa only)

The detailed PDP reference value for CDL-C UMa and CDL-C UMi validation are defined in the following tables:

Table C.3.2-3: PDP Targets for CDL-C UMa beam 1 at ≤ 2.5 GHz

Combined Clusters index	Delay(ns)	Power(dB)
1	0	-34.3
2-5	80	-19.5
6-8	235	0.0
9-10	290	-33.0
11	450	-35.8
12	480	-34.0

Table C.3.2-4: PDP Targets for CDL-C UMa beam 2 at ≤ 2.5 GHz

Combined Clusters index	Delay(ns)	Power(dB)
1	0	-27.9
2-5	80	0.0
6-8	235	-18.4
9-10	290	-27.8
11	450	-27.9
12	480	-28.0

Table C.3.2-5: PDP Targets for CDL-C UMa beam 1 at > 2.5 GHz

Combined Clusters index	Delay(ns)	Power(dB)
1	0	-34.2
2-5	80	-19.3
6-8	235	0.0
9	290	-34.7
10	450	-35.8
11	480	-34.7

Table C.3.2-6: PDP Targets for CDL-C UMa beam 2 at > 2.5 GHz

Combined Clusters index	delay(ns)	power(dB)
1	0	-27.8
2-5	80	0.0
6-8	235	-18.3
9-10	290	-28.9
11	450	-28.1
12	480	-28.8

Table C.3.2-7: PDP Targets for CDL-C UMi at ≤ 2.5 GHz and > 2.5 GHz

Combined Clusters index	Delay(ns)	Power(dB)
1	0	-30.7
2-5	20	-19.2
6-10	65	0
11-12	130	-31.4