E.2 Simulation model for generating packed delay and loss profiles

26.1323GPPRelease 18Speech and video telephony terminal acoustic test specificationTS

This clause describes a simulation model that generates packet arrival time variations and packet loss experienced by the receiving UE for MTSI-based speech with an end-to-end LTE access.

The model is derived solely for the purpose of testing the UE delay for MTSI-based speech with LTE access. As discussed in Section E.1, several LTE network parameters have a significant impact on the packet delay variations experienced by the UE. This model includes the effect of the DRX cycle, the BLER on the MAC/PHY layer, the HARQ re-transmission and RMC scheduler [46]. In addition, jitter in the EPC and the effect of the mis-alignment of the DRX-cycle between the uplink and downlink eNBs are included.

The model is described in Table E.1 and operates on the following input parameters

– Uplink and downlink block error rate (BLER), respectively.

– Maximum number of HARQ re-transmissions on uplink and dowblink, respectively.

– DRX cycle length.

– Time differnce between the uplink and the downlink eNB DRX cycle.

– Maximum and minimum network delay between the uplink and the downlink eNB.

The random number generator used in the model produces pseudorandom values drawn from the standard uniform distribution on the open interval (0, 1).

The model generates packet delay and loss profiles for two different test system configurations of the UE delay:

– When the system simulator is transparent in the downlink at the MAC/PHY layer and does not operate in DRX. This approach requires the variations of the delay due to downlink HARQ re-transmissions and mapping to the DRX cycle to be simulated. In this case, the model simulates the delay and jitter profiles for the packets from the antenna of the sending UE to the antenna receiving UE (end-to-end simulation). This is the testing condition used in 3GPP TS 26.132.

– When the system simulator is configured for error insertion in the downlink at the MAC/PHY layer and DRX operation, and the system simulator implements the HARQ re-transmissions and the mapping of the packets to the DRX cycle time at the downlink. In this case, the model simulates the delay and loss profiles from the sending UE up to the receiving eNB. This testing condition is currently not used in 3GPP TS 26.132.

It should be noted that the model does not fully utilize the PDB for QCI1 as defined in 3GPP TS 23.203 and does not include temporary variations of the packet arrival time variation and the loss rate that may be experienced during e.g. hand-over or congestion. Hence, the packet delay and loss profiles generated by the model do not fully exercise the conditions that the jitter buffer management of the UE may be exposed to in LTE systems and the profiles generated by the model are only intended for the testing of the UE delay in stationary operating conditions.

Table E.1: Simulation model for generating packet delay and loss profiles for MTSI-based speech with LTE access

function [UE1_UE2_dly,UE1_eNB2_dly,plr,comp_e2e,comp] = …

VoLTEDelayProfile_vPHY(BLER_tx, BLER_rx, max_tx, max_rx, drx_cycle_length, mis_eNB1_eNB2, max_net_delay, min_net_delay, nFrames, seed)

% BLER_tx : The block error rate in uplink.

% BLER_rx : The block error rate in downlink.

% max_tx : The maximum number of transmission attempts in uplink.

% max_rx : The maximum number of transmission attempts in downlink.

% drx_cycle_length : The length of the DRX cycle

% mis_eNB1_eNB2 : Scheduling time mis-alignment between eNB1 and eNB2

% max_net_delay : The maximum network delay between eNB1 to eNB2

% min_net_delay : The minimum network delay between eNB1 to eNB2

% nFrames : The number of frames for the simulation

% seed : Random number generator seed

rng(seed);

UE1_UE2_time = zeros(nFrames, 1);

UE1_eNB2_time = zeros(nFrames,1);

eNB1_eNB2_dly = round(min_net_delay + (max_net_delay-min_net_delay).*rand(nFrames,1));

ack1 = zeros(nFrames,1);

ack2 = zeros(nFrames,1);

wall_clock = 20;

frame = 1;

frame_size = 20;

simulationTime = nFrames*frame_size;

% Calculate the delay from UE1 speech encoder delivery to eNB2. If

% transmission to eNB1 is not successful after max_tx attempts, dly = 0 (packet loss)

while (wall_clock<=simulationTime)

% Set the scheduling time

if drx_cycle_length == 0

UE1_scheduling_time=wall_clock;

else

UE1_scheduling_time=ceil(wall_clock/drx_cycle_length)*drx_cycle_length;

end

% Add the tx effect for the scheduling time

n=0;

eNB1_receive_delay = 0;

while n < max_tx

if (rand(1) < BLER_tx)

eNB1_receive_delay = eNB1_receive_delay+8;

n=n+1;

ack=0;

else

ack=1;

n=max_tx;

end

end

while (wall_clock<=UE1_scheduling_time)

UE1_eNB2_time(frame)=ack*(UE1_scheduling_time+eNB1_receive_delay+eNB1_eNB2_dly(frame));

wall_clock=wall_clock+frame_size;

ack1(frame)=ack;

frame=frame+1;

end;

end

% Translate arrival time to packet delay for UL simulation

wall_clock = frame_size*(1:nFrames)’;

UE1_eNB2_dly = max(-1, UE1_eNB2_time-wall_clock);

% Sort for monotonic arrival time to DL for simulation

[UE1_eNB2_time,monotonic_index]=sort(UE1_eNB2_time);

% Calculate the delay from eNB2 to UE2 (only for those packets that

% successfully arrived at the eNB2!). If transmission to UE2 is not

% successful after max_tx attempts, dly = 0; (packet loss)

frame = 1;

UE2_scheduling_time=mis_eNB1_eNB2;

while frame<=nFrames

% Add the rx effect for the scheduling time

n=0;

eNB2_transmit_delay = 0;

while n < max_rx

if (rand(1) < BLER_rx)

eNB2_transmit_delay = eNB2_transmit_delay+8;

n=n+1;

ack=0;

else

ack=1;

n=max_rx;

end

end

while ((frame<=nFrames)&&(UE1_eNB2_time(frame)<UE2_scheduling_time))

if (UE1_eNB2_time(frame)==-1)

UE1_UE2_time(frame)=-1;

else

UE1_UE2_time(frame)=ack*(UE2_scheduling_time+eNB2_transmit_delay);

end

ack2(frame)=ack;

frame=frame+1;

end

% Update the scheduling time

UE2_scheduling_time=UE2_scheduling_time+drx_cycle_length;

end

% Re-order for orignal transmit order

UE1_UE2_time(monotonic_index) = UE1_UE2_time;

% Translate arrival time to packet delay

wall_clock = frame_size*(1:nFrames)’;

UE1_UE2_dly = max(-1, UE1_UE2_time-wall_clock);

% Set compensation values

if drx_cycle_length==0

comp_e2e=min_net_delay;

comp=min_net_delay;

else

comp_e2e=min(UE1_UE2_dly(UE1_UE2_dly>0));

comp=min(UE1_eNB2_dly(UE1_eNB2_dly>0));

end

% Calculates the overall packet loss from UE1 to UE2

pl=0;

for frame=1:nFrames

if UE1_UE2_dly(frame)==-1;

pl=pl+1;

end

end

plr=pl/nFrames;